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研究生: 李珮玟
Li, Pei-Wen
論文名稱: 5 GHz 電流再利用架構及 3.5 GHz 雜訊抵消架構之超低溫低雜訊放大器設計
Design of Cryo-CMOS LNA with a 5 GHz Current-Reuse Architecture and a 3.5 GHz Noise-Cancellation Architecture
指導教授: 黃尊禧
Huang, Tzuen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 137
中文關鍵詞: C-bandS-band低雜訊放大器電流再利用雜訊抵消量子電腦低溫應用低溫低雜訊放大器
外文關鍵詞: C-band, S-band, low-noise amplifier, current-reused, noise-canceling, quantum computer, cryogenic applications, Cryo-CMOS LNA
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  • 本論文大致分為兩個部分,分別為應用於 C-band 的 5 GHz 電流再利用低雜訊放大器電路以及 S-band 的 3.5 GHz 雜訊抵消低雜訊放大器電路,皆使用 TSMC 180-nm CMOS 製程,並且將電路設計應用於低溫環境中,確保電路在低溫環境下能夠正常運作。
    第一部分的 5 GHz 電流再利用低雜訊放大器電路,主要使用電流再利用技術、電感性源極退化技術以及順向基極自偏壓技術,達到高增益和低功耗特性,並且透過高增益壓抑後級的雜訊表現,藉由順向基極偏壓技術減緩電晶體的臨界電壓在低溫環境下上升的影響,而第二部分的 3.5 GHz 雜訊抵消低雜訊放大器電路,主要為雜訊抵消架構搭配基極自偏壓技術,透過回授電阻的方式,將第一級電晶體的雜訊在輸出端抵消,以及非線性項也以相同概念抵消,達到降低雜訊、提升線性度,並且使用基極自偏壓技術,使得電晶體在低溫環境下能正常操作,也能降低電路的功耗。在電路佈局方面,透過將主要訊號及電流路徑的走線以大片金屬的方式繪製,降低電路中的寄生電阻和寄生電容,量測方面皆以 on-wafer 的方式進行,並且將電路進行常溫及低溫量測 (包含 77 K、4 K),透過量測結果及模擬結果,進行分析及討論,並且驗證電路在常溫及低溫環境下的表現。

    This thesis can be mainly divided into two parts: a 5 GHz current-reused low-noise amplifier (LNA) circuit for the C-band and a 3.5 GHz noise-canceling LNA circuit for the S-band. Both designs utilize the TSMC 180-nm CMOS process and are intended for operation at cryogenic temperature, ensuring proper functionality under such conditions.
    The first part focuses on a 5 GHz current-reused LNA circuit, which employs current-reused techniques, inductive source degeneration, and forward-body biasing to achieve high gain and low power consumption. The high gain helps suppress noise from subsequent stages, while the forward-body biasing mitigates the increase in transistor threshold voltage at cryogenic temperatures. The second part presents a 3.5 GHz noise-canceling LNA circuit, which adopts a noise-canceling architecture combined with self-forward-body biasing. Using feedback resistors, the noise from the first-stage transistors is canceled at the output node, and the nonlinear components are simultaneously canceled, resulting in the reduction of noise and the improvement of linearity. The self-forward-body biasing also ensures proper transistor operation in cryogenic temperature environments and reduces circuit power consumption. In terms of layout, the primary signal and current paths are designed using wider metal traces to minimize parasitic resistance and capacitance. Measurements were conducted using on-wafer probing techniques, covering both room-temperature and cryogenic-temperature conditions (including 77 K and 4 K). The measurement results were compared with simulations for analysis and discussion, verifying the performance of the designed LNA circuits under both room-temperature and cryogenic-temperature environments.

    第一章 緒論 1 1.1 研究發展與動機 1 1.2 文獻回顧 5 1.3 論文章節架構概述 7 第二章 低雜訊放大器 (Low Noise Amplifier) 8 2.1 低雜訊放大器簡介 9 2.2 低雜訊放大器之重要參數 10 2.2.1 散射參數/ S 參數 (Scattering Parameter/ S Parameter) 10 2.2.2 雜訊 (Noise) 15 I. 熱雜訊 (Thermal noise) 16 II. 閃爍雜訊 (Flicker Noise) 18 III. 散粒雜訊 (Shot Noise) 19 2.2.3 線性度 (Linearity)[20] 22 I. 1 dB 增益壓縮點 (1 dB Gain Compression Point,P1dB) 22 II. 輸入三階截止點 (Input Third Order Intercept Point,IIP3) 23 2.2.4 穩定度 (Stability) 25 2.3 低雜訊放大器之基本架構 27 2.3.1 共閘極架構 (Common Gate) 27 2.3.2 電感性源極退化架構 (Inductive Source Degeneration) 29 2.3.3 電阻回授共源極架構 (Resistive Feedback Common Source) 31 2.4 低溫環境下的元件特性變化 33 2.4.1 主動元件 33 2.4.2 被動元件 36 第三章 電流再利用低雜訊放大器電路設計 39 3.1 研究背景與動機 39 3.2 電流再利用低雜訊放大器電路設計及實現 41 3.2.1 電路設計流程 41 I. 訂定預期規格並選擇架構 41 II. 電路設計及模擬 41 III. 電路佈局及模擬 42 3.2.2 規格探討 43 3.2.3 架構選擇與簡介 44 I. 電流再利用技術 45 II. 順向基極偏壓技術 47 III. 電感性源極退化技術 48 3.2.4 電路設計說明與考量 48 I. 電晶體偏壓訂定 48 II. 電晶體尺寸選擇 51 III. 加入被動元件 53 III. 面積及量測考量 54 3.3 電路佈局 55 3.4 模擬結果與探討 56 3.4.1 模擬結果 56 3.4.2 電路變異模擬結果 62 3.4.3 結論與探討 65 第四章 雜訊抵消低雜訊放大器電路設計 66 4.1 研究背景與動機 66 4.2 雜訊抵消低雜訊放大器電路設計及實現 67 4.2.1 電路設計流程 67 I. 訂定預期規格並選擇架構 67 II. 電路設計及模擬 68 III. 電路佈局及模擬 68 4.2.2 規格探討 68 4.2.3 架構選擇與簡介 70 I. 雙重回授電阻雜訊抵消架構 71 II. 基極自偏壓技術 73 4.2.4 電路設計說明與考量 73 I. 電晶體初步偏壓及尺寸訂定 73 II. 雜訊抵消架構 74 III. 輸入及輸出匹配 74 4.3 電路佈局 75 4.4 模擬結果與探討 77 4.4.1 模擬結果 77 4.4.2 電路變異模擬結果 81 4.4.3 結論與探討 84 第五章 室溫與低溫量測結果與討論 85 5.1 電流再利用低雜訊放大器電路室溫量測 85 5.1.1 室溫量測環境建置 85 5.1.2 量測結果與討論 87 5.2 雜訊抵消低雜訊放大器電路室溫量測 91 5.2.1室溫量測環境建置 91 5.2.2 量測結果與討論 91 5.2.3 電路改版設計及模擬 94 5.2.4 第二版電路量測結果與討論 99 5.3 低溫量測 103 5.3.1 低溫量測環境建置 103 5.3.2 電流再利用低雜訊放大器電路低溫量測結果與討論 106 5.3.3 第二版雜訊抵消低雜訊放大器電路低溫量測結果與討論 110 第六章 結論及未來展望 114 6.1 結論 114 6.2 未來展望 115 參考文獻 116

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