| 研究生: |
李珮玟 Li, Pei-Wen |
|---|---|
| 論文名稱: |
5 GHz 電流再利用架構及 3.5 GHz 雜訊抵消架構之超低溫低雜訊放大器設計 Design of Cryo-CMOS LNA with a 5 GHz Current-Reuse Architecture and a 3.5 GHz Noise-Cancellation Architecture |
| 指導教授: |
黃尊禧
Huang, Tzuen-Hsi |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2025 |
| 畢業學年度: | 113 |
| 語文別: | 中文 |
| 論文頁數: | 137 |
| 中文關鍵詞: | C-band 、S-band 、低雜訊放大器 、電流再利用 、雜訊抵消 、量子電腦 、低溫應用 、低溫低雜訊放大器 |
| 外文關鍵詞: | C-band, S-band, low-noise amplifier, current-reused, noise-canceling, quantum computer, cryogenic applications, Cryo-CMOS LNA |
| 相關次數: | 點閱:152 下載:50 |
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本論文大致分為兩個部分,分別為應用於 C-band 的 5 GHz 電流再利用低雜訊放大器電路以及 S-band 的 3.5 GHz 雜訊抵消低雜訊放大器電路,皆使用 TSMC 180-nm CMOS 製程,並且將電路設計應用於低溫環境中,確保電路在低溫環境下能夠正常運作。
第一部分的 5 GHz 電流再利用低雜訊放大器電路,主要使用電流再利用技術、電感性源極退化技術以及順向基極自偏壓技術,達到高增益和低功耗特性,並且透過高增益壓抑後級的雜訊表現,藉由順向基極偏壓技術減緩電晶體的臨界電壓在低溫環境下上升的影響,而第二部分的 3.5 GHz 雜訊抵消低雜訊放大器電路,主要為雜訊抵消架構搭配基極自偏壓技術,透過回授電阻的方式,將第一級電晶體的雜訊在輸出端抵消,以及非線性項也以相同概念抵消,達到降低雜訊、提升線性度,並且使用基極自偏壓技術,使得電晶體在低溫環境下能正常操作,也能降低電路的功耗。在電路佈局方面,透過將主要訊號及電流路徑的走線以大片金屬的方式繪製,降低電路中的寄生電阻和寄生電容,量測方面皆以 on-wafer 的方式進行,並且將電路進行常溫及低溫量測 (包含 77 K、4 K),透過量測結果及模擬結果,進行分析及討論,並且驗證電路在常溫及低溫環境下的表現。
This thesis can be mainly divided into two parts: a 5 GHz current-reused low-noise amplifier (LNA) circuit for the C-band and a 3.5 GHz noise-canceling LNA circuit for the S-band. Both designs utilize the TSMC 180-nm CMOS process and are intended for operation at cryogenic temperature, ensuring proper functionality under such conditions.
The first part focuses on a 5 GHz current-reused LNA circuit, which employs current-reused techniques, inductive source degeneration, and forward-body biasing to achieve high gain and low power consumption. The high gain helps suppress noise from subsequent stages, while the forward-body biasing mitigates the increase in transistor threshold voltage at cryogenic temperatures. The second part presents a 3.5 GHz noise-canceling LNA circuit, which adopts a noise-canceling architecture combined with self-forward-body biasing. Using feedback resistors, the noise from the first-stage transistors is canceled at the output node, and the nonlinear components are simultaneously canceled, resulting in the reduction of noise and the improvement of linearity. The self-forward-body biasing also ensures proper transistor operation in cryogenic temperature environments and reduces circuit power consumption. In terms of layout, the primary signal and current paths are designed using wider metal traces to minimize parasitic resistance and capacitance. Measurements were conducted using on-wafer probing techniques, covering both room-temperature and cryogenic-temperature conditions (including 77 K and 4 K). The measurement results were compared with simulations for analysis and discussion, verifying the performance of the designed LNA circuits under both room-temperature and cryogenic-temperature environments.
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