隨著摩爾定律的演進，尺寸微縮面臨嚴重的短通道效應，使得元件從平面演化至立體，多閘極結構閘極包覆通道的面積較大可以增加閘極控制力，其中鰭式場效電晶體為廣泛應用於半導體產業中，可有效抑制短通道效應且降低次臨界擺幅、降低漏電流及提高驅動電流。
在本篇論文中，先做P型矽鰭式電晶體的電性上量測，在使用TCAD模擬軟體驗證，先是進行不同尺寸理想P型電晶體的模擬，發現越小閘極長度的電晶體在Ioff、SS、DIBL值都越高，代表短通道效應明顯，符合電晶體特性。之後加入非理想效應的GIDL效應，在元件關閉時仍有漏電流的產生。在矽與二氧化矽介面處加入界面缺陷，在相同濃度下的缺陷，離導帶越遠(離價帶越近)的漏電流越大；在相同能階下，濃度越高的陷阱，漏電流越大。在不同通道濃度下發現通道濃度越高，驅動電流微微降低但漏電流卻明顯下降，因此電流開關比大。綜合以上，最後在距離導帶0.6eV、濃度為2×1016(cm-2eV-1)設定缺陷為最接近實驗數據趨勢的模擬，因此可以大約判斷實際元件在距離導帶0.6eV，2×1016(cm-2eV-1)濃度的缺陷(doner state)也有類似的缺陷。
SOI FinFET多了一層絕緣層導致散熱能力更差，使自我加熱效應更加嚴重，造成元件特性變差，故本篇再加入自我加熱效應來探討。在溫度高時，表面電位減少，曲線向右移導致臨界電壓較小。同時也造成漏電流上升、開關電流比下降、次臨界搖擺上升。

The extensive electrical characterization of the P-type silicon FinFET is conducted while the peculiar phenomena discovered are subsequently elucidated by running the TCAD simulation. First, the ideal P-type FinFETs of different sizes are simulated, and it is found that the values of Ioff, SS, and DIBL of the transistors are higher with the shorter gate length, evidently pointing to the short channel effect. Then, by introducing the non-ideal effects such as GIDL into the simulated model, the leakage current persists with a noticeable magnitude when the device is switched off. Another non-ideal effect under consideration is adding interface traps to the interface between silicon and silicon dioxide. When traps are at the same concentration, the traps that are farther from the conduction band (or closer to the valence band) redound to a larger leakage current; On the other hand, when traps are at the same energy level, the higher the trap concentration, the larger the leakage current.
Furthermore, if different channel concentrations are in the picture, it shows that with the higher channel concentration, a slight reduction in the saturated drain current ID(sat) is observed as compared to a sizable deduction in the leakage current, which engenders a larger on/off current ratio. Finally, if the trap with a concentration of 21016(cm-2eV-1) is set at a distance of 0.6 eV away from the conduction band, the closest match is found in terms of trend and magnitude between the experiment and simulation. Therefore, it is reasonable to conclude that the sample chip under study also has similar trap defects with a concentration of 21016(cm-2eV-1)and a distance of 0.6 eV from the conduction band (doner state).
The underlying buried oxide layer in SOI FinFET leads to a worse scenario in heat dissipation, making the self-heating effect more detrimental which would eventually give rise to poor electrical characteristics. Therefore, the self-heating effect must also be considered in the model. It is found that as the temperature increases, the surface potential decreases, which renders the threshold voltage smaller. Meanwhile, high temperature also leads to an increase in leakage current and subthreshold swing, and a decrease in on/off current ratio.

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