在本論文中，我們使用N型高壓金氧半場效電晶體(HV-MOSFETs)，討論其不同元件結構(對稱與非對稱結構)與相異輕摻雜之漂移區濃度對於元件特性與熱載子可靠度所造成的影響。
首先，會先闡述本篇論文的研究動機，並介紹高壓金氧半場效電晶體在現今社會的應用與其優點。由於高壓金氧半場效電晶體經常操作於高電壓的環境，探討熱載子可靠度與元件崩潰的物理機制是非常重要的議題，因此我們將說明熱載子效應與元件崩潰的基本機制。為了能夠更深入了解元件的物理機制，我們將使用電腦輔助設計TCAD模擬的方式進行分析與討論。
第二部分我們將呈現此研究的元件結構、其元件內部區域的定義與元件量測偏壓的設定，並透過基本電性的量測以觀察不同元件結構與相異輕摻雜之漂移區濃度所產生的影響，包括元件電流Id-Vg、截止態崩潰電壓VBD與基板電流Isub-Vg。
第三部分將討論不同閘極電壓對於元件熱載子退化的影響。前人的研究結果指出，在固定汲極電壓Vd的情況下，造成元件熱載子退化最嚴重的閘極電壓Vg將發生在產生Isub峰值之Vg或是使用較高的Vg，因此在固定的Vd情況下，我們針對這兩種閘極電壓進行熱載子加速測試，實驗結果顯示產生Isub峰值的閘極電壓將導致最嚴重的元件熱載子退化，我們推測此現象是來自於介面缺陷產生的位置與數量所造成的影響。除此之外，實驗結果亦顯示介面缺陷的產生將強化克爾克效應(Kirk effect)。
最後，我們將討論元件截止態崩潰電壓與熱載子生命週期在不同元件結構以及漂移區摻雜濃度之下的變化。實驗結果透露截止態崩潰電壓與元件結構較無關、與漂移區摻雜濃度較相關，而熱載子生命週期與兩者皆相關。隨著漂移區摻雜濃度越高，截止態崩潰電壓與熱載子生命週期皆有提升的趨勢。透過TCAD模擬發現適當提高摻雜濃度將增加元件臨界電場，有助於截止態崩潰電壓的改善；此外，提高漂移區摻雜濃度亦會改變導通電流的分布，並改善元件熱載子生命週期。

In this thesis, we will investigate the influence of different device structure (symmetric structure and asymmetric structure) and n- drift region doping concentration on the device characteristics and hot carrier reliability for the high voltage metal-oxide-semiconductor field-effect transistors (HV-MOSFETs).
First, we will describe the motivation of this thesis and introduce the application and advantages of HV-MOSFETs nowadays. Owing to the design for endurance of high voltage applied, it is an important issue for investigation of hot carrier reliability and off-state breakdown voltage mechanisms for HV-MOSFETs. In order to understand the physical mechanisms further, we will use technology computer-aided design (TCAD) for analyses and discussion.
The device structure, the definition of the device internal region, and the measurement setup are presented in the second part. In addition, the effect of the different device structure and n- drift region doping concentration are observed with the basic electrical measurements, including device current (Id-Vg), off-state breakdown voltage (VBD), and substrate current (Isub-Vg).
The third part is to investigate the influence of the different values of gate voltage (Vg) on the hot carrier degradation with fixed drain voltage (Vd). Several previous papers demonstrate that the Vg resulting in most severe hot carrier degradation is either the Vg producing peak substrate current (Isub) or higher Vg with the fixed Vd. Therefore, accelerated tests are performed under the various gate voltage with the fixed Vd. The results show that the Vg producing peak Isub will lead to more serious hot carrier degradation, which is suggested that this phenomenon is attributed to the amounts and location of the interface states (Nit). Besides, the experimental results also show that interface state generation will enhance Kirk effect.
Finally, the effects of different device structure and doping concentration in the drift region on the device off-state breakdown voltage and hot carrier lifetime are discussed. The results reveal that off-state breakdown voltage is less related to the device structure than doping concentration in the drift region. However, hot carrier lifetime is related to both of them. It can be found that a proper increase in doping concentration in the drift region will enlarge critical electric field, improving the off-state breakdown voltage. In addition to the off-state breakdown voltage, increasing doping concentration in the drift region also affects the distribution of conduction current and improves the device hot carrier lifetime.

[1] Y.H. Huang, P.J. Liao, Y.H. Lee , M.J. Chen, T.Y. Ho, and L. Chang Investigation of Kirk-Effect Induced Hot-Carrier-Injection in High-Voltage Power Devices 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 1-4, 2018.
[2] J.F. Chen, K.M. Wu, K.W. Lin, Y.K. Su, and S. L. Hsu Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual 560-4, 2005.
[3] Y.L. Tsai, J.F. Chen, S.F. Shen, H.T. Hsu, C.Y. Kao, K.F. Chang, and H.P. Hwang Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region Semiconductor Science and Technology 33 12 125019, 2018.
[4] Dhanoop Varghese, Muhammad Ashraful Alam, and Bonnie Weir A generalized, IB-independent, physical HCI lifetime projection methodology based on universality of hot-carrier degradation 2010 IEEE International Reliability Physics Symposium 1091-4, 2010.
[5] S. Roji Marjorie, P. A. Govindacharyulu, and K. Lal Kishore Studies on the dependence of breakdown voltages LDMOS devices on their structure and doping profiles of LDD regions 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics 42-5, 2012.
[6] X.R. Luo, J. Wei, X.L. Shi, K. Zhou, R.C. Tian, B. Zhang, and Z.J. Li Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage IEEE Transactions on Electron Devices 61 12 4304-8, 2014.
[7] S. Ogura, P.J. Tsang, W.W. Walker, D.L. Critchlow, and J.F. Shepard Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor IEEE Journal of Solid-State Circuits 15 4 424-32, 1980.
[8] J. Kim, S.G. Kim, T.M. Roh, J.G. Koo, and K.S. Nam A novel p-channel SOI LDMOS transistor with tapered field oxides Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212) 375-8, 1998.
[9] Susanna Reggiani, Stefano Poli, Elena Gnani, Antonio Gnudi, and Giorgio Baccarani Analysis of HCS in STI-based LDMOS transistors 2010 IEEE International Reliability Physics Symposium 881-6, 2010.
[10] J.F. Chen, T.J. Ai, Y.L. Tsai, H.T. Hsu, C.Y. Chen, and H.P. Hwang Analysis of high-voltage metal–oxide–semiconductor transistors with gradual junction in the drift region Japanese Journal of Applied Physics 55 8S2 08PD04, 2016.
[11] J.F. Chen, S.Y. Chen, K.S. Tian, K.M. Wu, Y.K. Su, C. M. Liu, and S. L. Hsu Effects of Drift-Region Design on the Reliability of Integrated High-Voltage LDMOS Transistors 2007 IEEE International Conference on Integrated Circuit Design and Technology 1-4, 2007.
[12] R.Y. Li, Y.S. Yang, F. Chen, L. Tang, Z.Y. Lv, B.H. Lee, L. Sun, W.Z. Xu, and T.C. Yu A study of 28nm LDMOS HCI improvement by layout optimization 2017 China Semiconductor Technology International Conference (CSTIC) 1-4, 2017.
[13] J.F. Chen, K.S. Tian, S.Y. Chen, K.M. Wu, and C.M. Liu On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region IEEE Electron Device Letters 29 9 1071-3, 2008.
[14] J. Kraft, B. Loffler, M. Knaipp, and E. Wachmann Hot Carrier Degradation of p-LDMOS Transistors for RF Applications 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual 626-7, 2007.
[15] M.L. Chen, C.W. Leung, W.T. Cochran, W. Jungling, C. Dziuba, and T.S. Yang Suppression of hot-carrier effects in submicrometer CMOS technology IEEE Transactions on Electron Devices 35 12 2210-20, 1988.
[16] C. Hu, Simon C. Tam, F.C. Hsu, P.K. Ko, T.Y. Chan, and K.W. Terrill Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement IEEE Journal of Solid-State Circuits 20 1 295-305, 1985.
[17] E. Takeda and N. Suzuki An empirical model for device degradation due to hot-carrier injection IEEE Electron Device Letters 4 4 111-3, 1983.
[18] J.H. Chen, S.C. Wong, and Y.H. Wang An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET IEEE Transactions on Electron Devices 48 7 1400-5, 2001.
[19] T.Y. Chan, J. Chen, P.K. Ko, and C. Hu The impact of gate-induced drain leakage current on MOSFET scaling 1987 International Electron Devices Meeting 718-21, 1987.
[20] K.W. Kim, C.S. Choi, and W.Y. Choi Analysis of a novel Elevated Source Drain MOSFET with reduced Gate-Induced Drain-Leakage current Proceedings 2000 IEEE Hong Kong Electron Devices Meeting (Cat. No.00TH8503) 36-9, 2000.
[21] B.S. Choi, H.N. Park, D.S. Kim, and B.D. Choi Improvement of drain leakage current characteristics in metal-oxide-semiconductor-field- effect-transistor by asymmetric source-drain structure 2012 IEEE International Meeting for Future of Electron Devices, Kansai 1-2, 2012.
[22] A. Hori, S. Kameyama, M. Segawa, H. Shimomura, and H. Ogawa A self-aligned pocket implantation (SPI) technology for 0.2μm-dual gate CMOS International Electron Devices Meeting 1991 641-4, 1991.
[23] L. Wang, J. Wang, C. Gao, J. Hu, P. Li; W.J. Li, and Steve H. Y. Yang Physical Description of Quasi-Saturation and Impact-Ionization Effects in High-Voltage Drain-Extended MOSFETs IEEE Transactions on Electron Devices 56 3 492-8, 2009.
[24] S.Y. Liu, W.F. Sun, H.W. Pan, H. Wang, and Q.S. Qian A novel latch-up free SCR-LDMOS for power-rail ESD clamp in half-bridge driver IC 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology 1-3, 2012.
[25] J. Deng and X.B. Chen A novel SCR-LDMOS for high voltage ESD protection 2015 IEEE 11th International Conference on ASIC (ASICON) 1-4, 2015.
[26] W.D. Nie, F.Y. Yi, and Z.G. Yu Kirk effect and suppression for 20 V planar active-gap LDMOS Journal of Semiconductors 34 5 054003, 2013.
[27] Mohamed Abouelatta-Ebrahim, Ahmed Shaker, Gihan T.Sayah, Christian Gontrand, and Abdelhalim Zekry Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study Ain Shams Engineering Journal 6 2 501-9, 2015.
[28] Silvaco, Inc. Atlas User Manual Santa Clara, CA, 2020.
[29] I.I. Shvetsov-Shilovskiy, et al. Measurement system for test memory cells based on keysight B1500A semiconductor device analyzer running LabVIEW software 2017 International Siberian Conference on Control and Communications (SIBCON) 1-4, 2017.
[30] T.Y. Chan, P.K. Ko, and C. Hu A simple method to characterize substrate current in MOSFET's IEEE Electron Device Letters 5 12 505-7, 1984.
[31] K.N. Quader, C.C. Li, R. Tu, E. Rosenbaum, P.K. Ko, and C. Hu A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation IEEE Transactions on Electron Devices 40 12 2245-54, 1993.
[32] T.Y. Chan, P.K. Ko, and C. Hu Dependence of channel electric field on device scaling IEEE Electron Device Letters 6 10 551-3, 1985.
[33] J.F. Chen, K.S. Tian, S.Y. Chen, K.M. Wu, J. R. Shih, and Kenneth Wu An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors IEEE Transactions on Device and Materials Reliability 9 3 459-64, 2009.
[34] Y.S. Lin, L.H. Chen, T.C. Chang, K.J. Liu, C.Y. Lin, and F.M. Ciou The Relationship Between Resistive Protective Oxide (RPO) and Hot Carrier Stress (HCS) Degradation in n-Channel LD SOI MOSFET IEEE Transactions on Electron Devices 68 3 962-7, 2021.
[35] C.Y. Lin, T.C. Chang, K.J. Liu, L.H. Chen, J.Y. Tsai, C.E. Chen, Y.H. Lu, H.W. Liu, J.C. Liao, and K.C. Chang Analysis of Contrasting Degradation Behaviors in Channel and Drift Regions Under Hot Carrier Stress in PDSOI LD N-Channel MOSFETs IEEE Electron Device Letters 38 6 705-7, 2017.
[36] Y.H. Huang, J.R. Shih, Y.H. Lee, S. Hsieh, C.C. Liu, K. Wu, and H.L. Chou Investigation of Monotonous Increase in Saturation-Region Drain Current during Hot Carrier Stress in N-type Lateral Diffused MOSFET with STI 2010 IEEE International Reliability Physics Symposium 170-4, 2010.
[37] W.F. Sun, C.W. Zhang, S.Y. Liu, T.T. Huang, C.H. Yu, W. Su, A.J. Zhang, Y.W. Liu, X.W. He, and X.W. Wu Hot-Carrier-Induced Forward and Reverse Saturation Current Degradations for the n-Type Symmetric EDMOS Transistor IEEE Electron Device Letters 35 7 690-2, 2014.
[38] J.M.C. Stork and R.D. Isaac Tunneling in base-emitter junctions IEEE Transactions on Electron Devices 30 11 1527-34, 1983.
[39] E. Hackbarth and D.D.-L. Tang Inherent and stress-induced leakage in heavily doped silicon junction IEEE Transactions on Electron Devices 35 12 2108-18, 1988.
[40] O.LeistikoJr.† and A.S.Grove Breakdown voltage of planar silicon junctions Solid-State Electronics 9 9 847-52, 1966.