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研究生： 葉俊邑
Yeh, Chun-Yi
論文名稱： 快閃式記憶體類神經網路SPICE模型開發與變異探討
SPICE Modeling for Flash Memory in Neural Networks and Variation Study
指導教授： 江孟學
Chiang, Meng-Hsueh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 64
中文關鍵詞： 快閃式記憶體 、精簡模型 、類神經網路 、Verilog-A 、HSPICE
外文關鍵詞： Flash, Compact Model, Neural Network, Verilog-A, HSPICE
相關次數： 點閱：208  下載：1 
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    • 隨著目前人工智慧以及物聯網的蓬勃發展下，馮紐曼架構無法有效的處以大量的數據，為了解決馮紐曼架構所帶來的瓶頸，記憶體內運算被視為打破此瓶頸的一大技術，快閃式記憶體為目前被廣泛討論的類神經網路的元件，具有成熟的製程技術、高位元密度及優秀的耐久度等優點，對於神經網路辨識很高的準確率。
    在本篇論文中，我們利用Verilog-A建立快閃式記憶體(Flash)模型，並以電路模擬軟體(HSPICE)測試電性，在快閃式記憶體操作中藉由給定不同電壓的脈衝波，使內部的浮柵存取電子，改變元件的閾值電壓高低。模型提供了不同多階操作功能。並且我們探討不同變異所造成的閾值電壓改變，提供各種變異在快閃式記憶體所造成的影響。此模型也提供模擬類比仿生網路的操作模式，並使用類比非揮發性記憶體電路平台，進行不同權重的訓練，達成手寫辨識的能力，最後展示不同脈衝波大小對於準確率的影響。

    With the flourishing development of Artificial Intelligence and the Internet of Things, the Von-Neumann architecture cannot handle large amounts of data efficiently. In order to solve the bottleneck of the Von-Neumann architecture, Computing In Memory (CIM) is regarded as a powerful technology to break this bottleneck. Flash memory is a widely discussed analog neural network device with mature process technology, high bit density, and excellent endurance. The accuracy in neural network recognition is very high.
    In this thesis, we developed a compact model of flash memory with physical characteristics using Verilog-A and obtained electrical characteristics through HSPICE simulations. In flash memory operation, the threshold voltage level of the device is changed by giving different voltages pulse to trap the electrons in the internal floating gate. The model provides different multilevel operation functions. Moreover, we investigate the effect of different kinds of variations on flash memory due to threshold voltage changes. The model also offers simulations for analog neural network operation patterns by using an analog nonvolatile memory circuit platform to train different weights to achieve handwriting recognition capability. Finally, we show the effect of different pulse sizes on the accuracy.

    摘要i Abstract ii 致謝iii Contents iv Table Captions vii Figure Captions viii Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Introduction of Simulation Tools 4 1.3.1 HSPICE 4 1.3.2 PSP Model Introduction 4 1.4 Overview of the Thesis 6 Chapter 2 Flash Introduction 7 2.1 Flash Structure 7 2.2 Fowler-Nordheim Tunneling 9 2.3 Channel Hot-Electron Injection 12 2.4 Read Operation 14 2.5 NOR Flash and NAND Flash Introduction 15 2.5.1 NOR Flash 15 2.5.2 NAND Flash 15 2.6 Single-Level Cell and Multi-Level Cell 17 2.6.1 Single-Level Cell 17 2.6.2 Multi-Level Cell 17 2.7 VT Distribution 18 Chapter 3 Flash Compact Model Construction 20 3.1 Capacitor Model for Flash Device 20 3.2 Channel Hot-Electron Injection Calculation 22 3.3 Fowler-Nordheim Tunneling Current Calculation 23 3.4 Simulation and Measurement Calibration 24 Chapter 4 Flash Variation Effect 27 4.1 MLC Simulation 27 4.1.1 Different Pulse Amplitude but Same Time 28 4.1.2 Different Number of Pulses at the Same Voltage 29 4.1.3 Incremental Step Pulse Programming (ISPP) 30 4.1.4 VT Distribution after Different program methods 31 4.2 Process Variation 33 4.2.1 Tunneling Oxide Variation 33 4.2.2 Oxide-Nitride-Oxide Variation 36 4.3 Input Variation 38 4.3.1 Gate Voltage Variation 38 4.3.2 Drain Voltage Variation 40 4.3.3 Pulse Width Variation 42 4.4 Temperature Variation 43 Chapter 5 Flash Model in Neural Network 51 5.1 Synapse Weight Equation 51 5.2 Synapse Characteristic Device 53 5.3 Simulation Result 53 Chapter 6 Conclusion and Future Work 60 6.1 Conclusion 60 6.2 Future Work 61 References 62

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