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研究生： 蔡俐萱
Tsai, Li-Xuan
論文名稱： 超低功耗喚醒接收器採用高轉換增益及高靈敏度包絡檢測器
An Ultralow-Power Wake-Up Receiver with High Conversion Gain and High Sensitivity Envelope Detector
指導教授： 鄭光偉
Cheng, Kuang-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 77
中文關鍵詞： 喚醒接收機 、超低功耗 、ISM頻段 、正回授包絡檢測器 、閥值可調比較器
外文關鍵詞： wake-up receiver, ultra-low power, ISM band, positive feedback envelope detector, programmable threshold comparator
相關次數： 點閱：125  下載：0 
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    • 本論文實現一個操作在ISM頻帶(Industrial Scientific Band), 可接收並解調振幅鍵控調變(ASK)的超低功耗喚醒接收器。在喚醒接收機的架構方面，採用直接偵測的架構以包絡檢測器實現訊號解調，並捨棄高功耗的射頻前端低雜訊放大器並利用高品質因數的外部電感提高電壓的增益，藉此實現超低功耗的喚醒接收器。
    在包絡檢測器方面，提出了藉由正回授的架構，藉由調整迴路增益達到高轉換增益，並同時考量雜訊及轉換增益，對整體的喚醒接收機進行優化。當訊號藉由包絡檢測器解調過後，在利用比較器還原輸入的喚醒碼，並透過16-bits的相關器增加喚醒接收的靈敏度，而當比較與目標喚醒碼的相關性。當相關性超過所設定的位元時，即產生喚醒訊號。而考量到喚醒接收器屬於大部分的時間都不會有輸入訊號的運作機制，在等待喚醒碼進入的同時，可能會因為環境的干擾而造成誤判進而送出喚醒訊號，因此在比較器方面採用閥值可調的架構以抵抗環境的干擾。包絡檢測器的迴路增益、目標喚醒碼以及比較器閥值皆由一個數位合成的SPI 所設定。本設計使用台積電提供的0.18微米CMOS製程。此喚醒接收機在加入編碼增益後預期在433百萬赫茲及2.4億赫茲分別可達到-67.1 dBm 及-61.1 dBm的靈敏度。供應電壓為0.6伏特時，消耗46.2毫微瓦。

    This thesis presents an ultra-low power wake-up receiver (WuRx). This WuRx operates in Industrial Scientific Band (ISM) and can demodulate the on-off keying (OOK) modulated wake-up signal. In this work, a detector-first architecture and an external high Q inductance be used to achieve the ultralow power and high voltage gain in RF, respectively.
    The envelope detector (ED) with positive feedback to enhance its conversion gain is proposed. The loop gain of the ED can be programmable to overcome the process variation. Following the ED, a programmable threshold comparator is used to recover the baseband signal, and a 16-bit correlator to enhance the sensitivity. When the correct bits are greater than threshold value, a wake-up signal will be generated. Considering the operation of the wake-up receiver in the low SNR situation, it will cause the false alarm. A programmable threshold comparator is used to avoid false alarms. Set the reference code of the WuRx receiver, the loop gain of the ED, and the threshold of the comparator through the SPI. This chip is fabricated in 0.18 μm TSMC technology. The WuRx operating at 433MHz and 2.4GHz with 10 kbps and an expected sensitivity with coding gain is -67.1 dBm and -61.1 dBm, respectively. The power consumption is 46.2nW under a 0.6-V supply voltage.

    List of Figure V List of Tables VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Wake-up Receiver (WuRx) Design Considerations 4 1.2.1 Sensitivity Specification 4 1.2.2 Power Budget 6 1.3 Thesis Organization 7 Chapter2 Literature Review of Low Power Wake-up Receiver 8 2.1 System Considerations 8 2.1.1 Uncertain-IF Architecture 8 2.1.2 Tuned RF Architecture 9 2.1.3 Detector-first Architecture 10 2.2 Types of Envelope Detector (ED) 11 2.2.1 Passive Envelope Detector 12 2.2.2 Noise of passive detector 13 2.2.3 Active Envelope Detector 14 2.2.4 Noise of active detector 16 2.3 Conclusions 17 Chapter3 Proposed WuRx and Circuit Designs 18 3.1 Introduction 18 3.2 Proposed Envelope Detector Architecture 19 3.2.1 Design Considerations 19 3.2.2 Feedback Theory Analysis 22 3.2.3 Conversion Gain and Stability 29 3.2.4 Noise Analysis and Sensitivity 33 3.2.5 Simulation Results of Proposed envelope Detector 37 3.3 Programmable Threshold Comparator 46 3.4 Correlator 53 Chapter4 Simulation of WuRx and Measurement 56 4.1 Simulation of Proposed WuRx System 56 4.1.1 Pre-simulation 57 4.1.2 Layout Consideration 59 4.1.3 Post-simulation of Proposed WuRx System 60 4.2 Test Setup and Measurement Result 62 4.2.1 Matching Network 64 4.2.2 Conversion Gain 66 4.2.3 Programmable Threshold Comparator Test 67 4.2.4 Sensitivity and Wake-Up Test 68 4.3 Conclusion 71 Chapter5 Conclusion and Future Work 73 5.1 Conclusion 73 5.2 Future Work 74 Reference 76 List of Figure Figure 1. 1 Conceptual diagram of WSNs 1 Figure 1. 2 Illustration of Duty-cycle communication 2 Figure 1. 3 Communication using wake-up receiver [18] 3 Figure 1. 4 SNR improve by coding gain 5 Figure 2. 1 Uncertain-IF wake-up receiver architecture[18] 8 Figure 2. 2 Uncertain-IF frequency plan and method of operation [18] 9 Figure 2. 3 Tuned RF architecture 9 Figure 2. 4 The detector-first wake-up receiver architecture 10 Figure 2. 5 Dickson detector 12 Figure 2. 6 RF matching network for passive detector 12 Figure 2. 7 Dickson detector (a) schematic and (b) baseband model 13 Figure 2. 8 Common-source detector 14 Figure 2. 9 Self-biased common source detector 15 Figure 2. 10 Simplified noise model of the self-biased common source detector 16 Figure 3. 1 Proposed wake-up receiver 18 Figure 3. 2 Tapped capacitor matching network 19 Figure 3. 3 A high conversion gain envelope detector based on positive feedback architecture. 20 Figure 3. 4 Self-bias ED with source degeneration Zs1 21 Figure 3. 5 Feedback network of proposed ED. 22 Figure 3. 6 Conceptual diagram of the proposed positive feedback ED 23 Figure 3. 7 Small signal analysis of closed-loop output impedance. 23 Figure 3. 8 Small signal analysis of open loop output impedance. 24 Figure 3. 9 Small signal analysis of feedforward amplifier 26 Figure 3. 10 Small signal analysis of feedback network. 28 Figure 3. 11 Feedback resistance expressed in multiples of the gm of M1 30 Figure 3. 12 The gm1 is attenuated by Zs1 31 Figure 3. 13 Baseband signal feedback path 32 Figure 3. 14 Noise model of the open loop circuit 34 Figure 3. 15 Noise concept block diagram for closed loop 34 Figure 3. 16 Envelope detector based on positive feedback architecture. 37 Figure 3. 17 Influence of ms and mf on g'm1,2nd 37 Figure 3. 18 The response of loop gain between ms and mf. 38 Figure 3. 19 Influence of ms and mf on MGnc 39 Figure 3. 20 Phase margin of the open loop 39 Figure 3. 21 Conversion gain (Gnc) and noise (No,ED) of ED 40 Figure 3. 22 The best signal to noise ratio 40 Figure 3. 23 Frequency response at Ved 41 Figure 3. 24 Calculation result of the closed-loop output impedance 41 Figure 3. 25 Simulation result of the closed-loop output impedance 42 Figure 3. 26 Calculation of proposed ED conversion gain 42 Figure 3. 27 Off-chip matching network with high-Q inductor 43 Figure 3. 28 Simulation result of S11 for (a)433 MHz, and (b)2.4 GHz 44 Figure 3. 29 AC simulation for (a)433 MHz, and(b)2.4 GHz matching network 44 Figure 3. 30 Improvement of (a) conversion gain and (b) sensitivity 45 Figure 3. 31 Sensitivity of post-simulation (a) in 433 MHz and (b) 2.4 GHz, respectively. 45 Figure 3. 32 Two-stage comparator [14] 46 Figure 3. 33 Programmable threshold comparator 47 Figure 3. 34 Control switch of comparator 48 Figure 3. 35 Control signal and threshold voltage in Cs=0 49 Figure 3. 36 Control signal and threshold voltage in Cs=1 50 Figure 3. 37 Comparator simulation setup 51 Figure 3. 38 Case 1: Output voltage of ED is close to the noise floor. 51 Figure 3. 39 Case 2: Increase the threshold of the comparator. 52 Figure 3. 40 Conceptual diagram of correlator 53 Figure 3. 41 Schematic of the correlator. 54 Figure 3. 42 Transmission-gate flip flop 54 Figure 4. 1 Block diagram of the wake-up receiver 56 Figure 4. 2 The Sensitivity improvement by the correlator tolerance setting 57 Figure 4. 3 Simulation result of wake-up receiver 58 Figure 4. 4 Layout of Wake-up Receiver 59 Figure 4. 5 S11 at (a)433 MHz and (b)2.4 GHz 60 Figure 4. 6 AC simulation for (a)433 MHz, and(b)2.4 GHz matching network 60 Figure 4. 7 Post-simulation result of wake-up receiver at 433MHz 61 Figure 4. 8 Die photograph of the WuRx 62 Figure 4. 9 (a) Schematic of PCB, and (b) its layout 63 Figure 4. 10 Schematic of measurement setup 64 Figure 4. 11 Schematic of measurement setup for input impedance 64 Figure 4. 12 The measurement result of input impedance 65 Figure 4. 13 Input matching in (a) 433MHz and (b) 2.4GHz 65 Figure 4. 14 Waveform of the ED output (Vbb_buf) when the input power is -45dBm (a)R2 is 572 kΩ (b) R2 is 40 kΩ in 433MHz 66 Figure 4. 15 Dynamic range of (a)simulation (b) measurement 66 Figure 4. 16 Voltage gain from Ved to Vbb 67 Figure 4. 17 The original comparator offset 68 Figure 4. 18 The result of the threshold control 68 Figure 4. 19 BER measurement setup 68 Figure 4. 20 synchronization of the data and the clock 69 Figure 4. 21 Sensitivity measurement (BER<10-3) of the WuRx in 433 MHz 69 Figure 4. 22 Measurement setup for wake-up test. 70 Figure 4. 23 Received the same data packet as the reference code 70 Figure 4. 24 Wake-up test with correlator tolerance is 0 bits 70 Figure 5. 1 RF signal line on the PCB 74 Figure 5. 2 The schematic of the simulation 74 Figure 5. 3 Simulation result of the input admittance 74 List of Tables Table 1. 1 Nano-watt level wake-up receiver 6 Table 3. 1 Comparison result between calculation and simulation 44 Table 3. 2 Power consumption of the corner simulation 45 Table 3. 3 The control signal and threshold voltage 49 Table 3. 4 The control signal codes and the related threshold voltage 50 Table 3. 5 Operation of the correlator 55 Table 3. 6 Power consumption 55 Table 4. 1 Power contribution 71 Table 4. 2 Simulation and measurement comparison table 71 Table 4. 3 Comparison table 72

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