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研究生：	歐育綸 Ou, Yu-Lun
論文名稱：	具PD-BII之10位元100MS/s導管式類比數位轉換器 A 10-bit 100MS/s Pipelined A/D Converter with PD-BII
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	72
中文關鍵詞：	導管式類比數位轉換器
外文關鍵詞：	pipelined A/D converter
相關次數：	點閱：108 下載：4
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本論文使用TSMC 0.18微米一層多晶矽六層金屬之互補式金氧半製程來實現一個十位元解析度、每秒取樣一百百萬次的低功率導管式類比數位轉換器。具有擬差動偏壓及輸入互換架構的運算放大器被用來取代運算放大器共享方式達到低功率消耗。擬差動運算放大器藉由輸入與偏壓互換的機制使其運作方式等效兩顆運算放大器，因此在每周期運算放大器的加成點可被重置。此外移除前端取樣保持電路與每級電容縮減最佳化更進一步節省功率與面積。根據post-layout的模擬結果，該類比數位轉換器操作在100MHz之取樣頻率，給予42.1875MHz的輸入訊號時，最大雜訊及諧波失真比為58.2dB、無雜散動態範圍為61.0dB。整體電路有效面積0.5mm2、在供應電壓1.8伏下功率消耗24.75mW。

A low power 10-bit 100-MHz pipelined ADC was implemented in a TSMC 0.18-μm 1P6M CMOS process in this thesis. Opamps with pseudo differential bias and input interchanging (PD-BII) architecture are used as alternatives to opamp-sharing scheme for low power consumption. Since PD-BII opamp with bias and input interchange performs as two opamps, the opamp summing nodes can be reset in every clock cycle. Further power and area savings can be achieved by removing the front-end sample-and-hold and capacitor scaling optimization. According to post-layout simulation, this ADC achieves 58.2-dB peak signal-to-noise plus distortion ratio (SNDR) and 61.0-dB spurious free dynamic range at a 42.1875MHz input with 100MS/s. The ADC occupies an active die area of 0.5mm2 and dissipates 24.75mW on a 1.8V supply.

Introduction   1
1	Motivation   1
2	Organization	  2

Review of Analog-to-Digital Converter   4
1	Fundamentals of Analog-to-Digital Converter   4
2	ADC Performance Metrics   5
2.1	Signal-to-Noise Ratio (SNR)   5
2.2	Total Harmonic Distortion(THD)   8
2.3	Signal-to-Noise and Distortion Ratio (SNDR)   8
2.4	Spurious Free Dynamic Range (SFDR)   8
2.5	Effective Number of Bits (ENOB)	  9
2.6	Nonlinearity   9
3	Review of ADC Architectures   11
3.1	Flash ADC   11
3.2	Two-Step ADC    12
3.3	Pipelined ADC   12
3.4	Cyclic ADC   13
4	Key Building Blocks of Pipelined ADC   14
4.1	Front-End Sample-and-Hold Circuit   14
4.2	Multiplying Digital to Analog Converter   17
4.3	Sub-ADC   18
4.4	Digital Error Correction   18
5	Summary	   20
	
System Analysis and Design of Pipelined ADC   21
1	Effects of Nonidealities   21
1.1	Gain Errors   22
1.2	DAC Errors   25
1.3	Nonlinearity   26
1.4	Opamp Incomplete Settling Time   28
1.5	Thermal Noise   28
2	Accuracy Requirements   30
2.1	Opamp DC Gain Requirement   30
2.2	Opamp Bandwidth Requirement   32
3	Opamp Sharing Technique   35
4	Capacitor Scaling Analysis and Optimization   38
	
Circuit Implementation   41
1	Architecture Description   41
2	Removing Front-End Sample-and-Hold Circuit   42
3	Multiplying Digital to Analog Converter   44
3.1	Gain-Boosted Cascode Amplifier   45
3.2	Switch Design   48
4	Comparator   51
5	Sub-ADC and Control Logic   53
6	Digital Error Correction   55
7	Non-overlapping Clock Generator   56
8	Layout and Floor Plan   58
9	Simulation Results of Pipelined ADC   60
10	Summary   62
	
Measurement Environment Setup   63
1	Test Setup   63
2	Power Supply and Ground   64
3	Reference Voltage Generator   65
	
Conclusion and Future Work   68
        
        Reference   69

                                    

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校內：2013-02-02公開
校外：2013-02-02公開

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