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研究生: 郭育禎
Kuo, Yu-Chen
論文名稱: 40V N型通道橫向擴散金氧半電晶體特性及其熱載子可靠度之研究
Characteristics and Hot Carrier Reliability in 40V n-type LDMOS Transistors
指導教授: 陳志方
Chen, Jone-Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 69
中文關鍵詞: 熱載子可靠度橫向擴散金氧半場效電晶體
外文關鍵詞: hot carrier reliability, LDMOS
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  • 本篇論文主要目的是對不同元件尺寸n型通道橫向擴散金氧半場效電晶體(LDMOSFET)之元件特性及熱載子可靠度(hot carrier reliability),做更深入的研究與探討。本論文使用的元件主要有四個尺寸參數:通道長度、累積區長度、受閘極控制的漂移區長度、未受閘極控制的漂移區長度。
    對元件特性來說,通道長度和累積區長度的影響比受閘極控制的漂移區長度和未受閘極控制的漂移區長度來的重要。而且導通電阻(Ron),靜態崩潰電壓(BVoff)以及累積區長度之間則呈現不符合預期的結果,此現象可以利用電腦輔助模擬(TCAD)實驗加以解釋。接著我們選擇一組標準的元件尺寸,進行定電壓的熱載子stress實驗並討論熱載子退化現象和退化機制。實驗結果發現不同的stress偏壓條件之下將導致導通電阻產生不同的退化斜率。藉由TCAD模擬以及charge pumping的分析,在不同stress條件下之退化機制可被完整的探討和統整。
    除此之外,元件尺寸對於元件導通電阻之生命期(Ron lifetime)的影響也會討論。其中改變累積區的長度對生命期的影響最為劇烈。所以我們將探討累積區尺寸對於導通電阻及飽和電流(Idsat)之退化機制。並且藉由TCAD模擬以及charge pumping的分析佐證退化結果。
    最後,將元件特性和熱載子stress實驗做比較後。我們也更加確認無論是考慮性能或是熱載子可靠度,累積區的長度都具有相當大的影響。此結果對於橫向擴散金氧半場效電晶體之元件設計將具有相當大的幫助。

    In this thesis, device characteristics and hot carrier reliability of n-type LDMOS transistors with different device dimension are investigated. The device used in this thesis has four main layout parameters: channel length, accumulation length, length of drift region with gate control and length of drift region without gate control.
    As for device characteristics, the effect of parameters of channel length and accumulation length are more significant than that of parameters of drift region with gate control and length of drift region without gate control. The unexpected connection between Ron, BVoff and accumulation length can be explained by TCAD Simulation. Then we choose a standard device dimension to perform constant voltage hot carrier stress and discuss the hot carrier degradation phenomenon and mechanism. The degradation of Ron reveals different power index of degradation for different stressed bias. By means of TCAD simulation and charge pumping analysis, the phenomenon of anomalous degradation can be discussed and explained in detail.
    Besides, effects of device dimension on Ron lifetime are investigated. Among prodigious enhancement of lifetime is certain as accumulation length increased. So, accumulation length is reduced and the effect of this change on Ron and Idsat are discussed. Charge pumping analysis and TCAD simulation are used to evidence for the stress experimental results.
    Finally, compare with device characteristics and hot carrier stressed experiments. We can conclude that accumulation length is an important concern in this device when considering both device performance and hot carrier reliability. Such an analysis can provide useful feedback in designing LDMOS devices.

    Contents Abstract (Chinese) I Abstract (English) III Acknowledgements V Contents VI Figure Captions VIII List of Tables XI Chapter 1 Introduction 1.1 Application of LDMOS Transistors 1 1.2 Introduction to hot carrier effect 2 1.3 Introduction to Taguchi method 3 1.4 About the thesis 3 Chapter 2 Measurement & Discussions of device characteristics 2.1 Introduction 10 2.2 Measurement Methodology 10 2.2.1 Measurement setup 10 2.2.2 Id-Vg measurement 10 2.2.3 Id-Vd measurement 11 2.2.4 Breakdown voltage measurement 12 2.3 Device description 12 2.4 Effect of dimension on device characteristic 13 2.5 Summary 14 Chapter 3 Degradations and mechanisms with hot carrier stress 3.1 Introduction 26 3.2 Experiment methodology & Stress conditions 26 3.3 Experimental results 27 3.3.1 Effect of Vg on parameter shift 27 3.3.2 Two stage degradation phenomenon 28 3.3.3 Ron degradation mechanism 28 3.4 Charge pumping analysis 29 3.4.1 Introduction to charge pumping theory 29 3.4.2 Experiment 31 3.4.3 Experimental results & discussions 32 3.5 Discussions the saturated phenomenon on Not 33 3.6 Summary 33 Chapter 4 Effects of device dimension on hot carrier reliability 4.1 Introduction 49 4.2 Experiment 49 4.3 Analysis of Experimental results 50 4.3.1 Effect of dimension (L, b, c, a) on lifetime shift 50 4.3.2 Effect of b on Ron degradation 50 4.3.3 Effect of b on Idsat degradation 51 4.4 Summary 54 Chapter 5 Conclusion and future work 5.1 Conclusion 63 5.2 Future work 64 References 66

    References
    [1] C. Contiero, P. Galbiati, and M. Palmieri, “Characteristics and applications of a 0.6μm Bipolar-CMOS-DMOS technology combing VLSI nonvolatile memories,” IEDM Tech. Dig., pp. 465-468 (1996).
    [2] K. Nakamura, T. Naka, K. Matsushita, Y. Matsudai, N. Yasuhara, K. Endo, F. Suzuki, and A. Nakagawa “Optimization of 5V power device based on CMOS for hot-carrier degradation,” International Symposium on Power Semiconductor Device & IC’s, PP. 335-338 (2005).
    [3] C. Y. Tsai, T. Efland, S. Pendharkar, J. Mitros, A. Tessmer, J. Smith, J. Erdeljac, L. Hutter, “16-60 V rated LDMOS show advanced performance in an 0.72 μm evolution BiCMOS power technology,” IEDM Tech. Dig., pp. 367-370 (1997).
    [4] V. Parthasarathy, R. Zhu, W. Peterson, M. Zunino, R. Baird, “A 33 V, 0.25 mΩ*cm2 n-channel LDMOS in a 0.65 μm smart-power technology for 20-30 V operation,” ISPSD, pp. 61-64 (1998).
    [5] J. A. Pol, A.W. Ludikhuize, H. G. A. Huizing, B. V. Velzen, R. J. E. Hueting, J.F. Mom, G. V. Lijnschoten, G.J.J. Hessels, E.F. Hooghoudt, R. V. Huizen, M.J. Swanenberg, J.H.H.A. Egbers, F. V. D. Elshout, J.J. Koning, H. Schligtenhorst, J. Soeteman, “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” ISPSD, pp. 327-330 (2000).
    [6] T. Terashima, F. Yamamoto, H. Hatasako, “Multi-voltage device integration technique for 0.5μm BiCMOS and DMOS process,” ISPSD, pp. 331-334 (2000).
    [7] A. W. Ludikhuize, M. Slotboom, A. Nezar, N. Nowlin, and R. Brock, “Analysis of hot-carrier-induced degradation and snapback in submicron 50V lateral MOS transistors,” ISPSD, pp. 53-56 (1997).
    [8] S. Aresu, W. D. Ceuninck, G. V. D. bosch, G. Groeseneken, p. Moens, J. Manca, D. Wojciechowski, P. Gassot, “Evidence for source side injection hot carrier effects on lateral DMOS transistors,” Microelectronics & Reliability, vol.44, pp. 1621-1624 (2004).
    [9] P. L. Hower, “Safe Operating Area-a New Frontier in LDMOS Design, ” ISPSD, pp. 1-8 (2002).
    [10] C. Hu, “Advanced MOS Device Physics,” in VLSI Electronic Microstructure Science, 18, Academic Press, New York, Chapter3 (1989).
    [11] C. Y. Chang and S. M. Sze, “ULSI Technology,” (1996).
    [12] J. Wiley and G. Taguchi, “The Mahalanobis-Taguchi strategy: a pattern technology system,” (2002).
    [13] D. Brisbin, P. Lindorfer and P. Chaparala, “Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices,” IEEE Transactions on Device and Materials Reliability, vol.6, pp. 364-370 (2006).
    [14] J. L. Lin, C. I. Lin and L. J. Lin, ”Modeling and Characteristic Analysis of Silicon-on-Insulator Lateral-Double-Diffusion Metal Oxide Semiconductor,” Japanese Journal of Applied Physics vol.47, pp. 8243-8247 (2008).
    [15] M. Zitouni, “A new lateral power MOSFET for smart power ICs:”LUDMOS concept,” Microelectronics Journal 30, pp.551-561 (1999).
    [16] K. M. Wu, Jone F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu and J. R. Shih, “Anomalous Reduction of Hot-Carrier-Induced ON-Resistance Degradation in n-Type DEMOS Transistors,” IEEE Transactions on Device and Materials Reliability, vol.6, pp.371-376 (2006).
    [17] F. Bauwens and P. Moens, “Locating hot carrier injection in n-type DeMOS transistors by Charge Pumping and 2D device simulations,” Microelectronics & Reliability, vol.44, pp. 1625-1629 (2004).
    [18] P. Moens, F. Bauwens and M. Thomason, “Two-stage Hot Carrier Degradation of LDMOS Transistors,” Proceedings of the 17th International Symposium on Power Semiconductor Devices & IC’s , pp. 323-326 (2005).
    [19] E. Takeda, C. Yang, A. Miura-Hamada, “Hot-carrier effects in MOS Devices,” Academic Press (1995).
    [20] A. Melik-Martirosian and T. P. Ma, “Improved charge-pumping method for Lateral Profiling of interface traps and oxide charge in MOSFET Devices,” IEDM, pp. 93-96 (1999).
    [21] D. K. Schroder, “Semiconductor Material and Device Characterization,” third edition (2006).
    [22] C. C. Cheng, K. C. Tu, and T. Wang, “Investigation of Hot Carrier Degradation Modes in LDMOS by Using A Novel Three-region Charge Pumping Technique,” IEEE IRPS, pp. 334-337 (2006).
    [23] C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and characterization of various hot-carrier degradation modes in LDMOS by using a novel three-region charge pumping technique,” IEEE TDMR, vol. 6, NO. 3, pp. 358-362 (2006).
    [24] K. S. Tian, J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Lee, T. Y. Huang, C. M. Liu, and S. L. Hsu, “An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistors,” Japanese Journal of Applied Physics vol.47, pp. 2641-2644 (2008)
    [25] S. Y. Chen, J. F. Chen, J. R. Lee, K. M. Wu, C. M. Liu, and S. L. Hsu, “Anomalous Hot-Carrier-Induced Increase in Saturation-Region Drain Current in n-Type Lateral Diffused Metal-Oxide-Semiconductor Transistors,” IEEE Transistors on Electron Devices, vol. 55, NO. 5, pp. 1137-1141 (2008).
    [26] I. K. Lee, S. R. Yun, K. S. Kim, C. G. Yu, and J. T. Park, “New Experimental Findings on Hot-Carrier-Induced Degradation in Lateral DMOS Transistors,” Microelectronics & Reliability, vol.46, pp. 1864-1867 (2006).

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