| 研究生: |
吳持若 Wu, Chi-Ruo |
|---|---|
| 論文名稱: |
應用於憶阻器實現神經形態工程學之考量熱能最佳化 Thermal Optimization for Memristor-Based Hybrid Neuromorphic Computing Systems |
| 指導教授: |
林英超
Lin, Ing-Chao |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2015 |
| 畢業學年度: | 103 |
| 語文別: | 英文 |
| 論文頁數: | 35 |
| 中文關鍵詞: | 憶阻器 、神經網路 、神經形態工程學 、譜聚類技術 |
| 外文關鍵詞: | memristor, neural network, neuromorphic computing system, spectral clustering technique |
| 相關次數: | 點閱:102 下載:6 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
神經形態工程學是使用超大型積體電路來實現並加速模擬動物大腦的神經網路,其中包含有神經元和突觸,神經元藉由突觸交換彼此的資訊以模擬人類的大腦。然而,傳統的電腦幾乎都依循著范紐曼(Von Neumann)提出的架構,但是將高頻率的中央處理器和記憶體分開會衍生出范紐曼瓶頸,即是資料在中央處理器和記憶體之間的傳輸速度跟不上前者的運算速度。因此,做為同時可以進行運算和儲存資料的憶阻器,被視為可以應用在未來電路上以解決此一問題的新興技術,此外,憶阻器擁有諸如低耗能、平行化運算、小體積和非揮發性等適合運用在神經形態工程學的特性。但是憶阻器的可靠度會被電壓衰退及熱能等因素影響,為了使神經網路有較高的可靠度,必須考量產生最多熱能的憶阻器,並且可以將其視為最大功率問題,因此我們提出了應用於憶阻器實現神經形態工程學之考量熱能譜聚類技術。實驗結果顯示我們提出的方法可以有效的降低系統中的最大功率。
Neuromorphic computing is used for accelerating the computation of neural network which can simulate the brain of animal and composed by neurons and synapses. However, the neuromorphic computing with the traditional computer architecture leads to serious von Neumann bottleneck because of the gap between high frequency CPU computation and memory access. The emerging memristor is an innovation technology for future VLSI circuits potentially can be acted as both data storage and computing unit to transform the computer architecture. Furthermore, the characteristics of memristors include low programming energy, parallel process, small footprint, non-volatility, etc, which have attracted significant researches on neuromorphic computing. However, some important issues such as thermal damage defect the reliability of memristors. High thermal of memristor is a critical issue which impacts the reliability of the systems. To estimate the thermal of the memristor, we formulated the thermal as the power consumption problem. In this thesis, a thermal optimization algorithm for memristor-based hybrid neuromorphic computing system is proposed to solve the the reliability issue by the incremental cluster network flow. Our results show that the maximum power consumption can be reduced about 31%.
[1] M. Hu et al, ”Hardware realization of BSB recall function using memristor crossbar arrays,” Proc. ACM/IEEE Design Autom. Conf., pp. 498–503, 2012.
[2] S. L. Bade and B. L. Hutchings, ”FPGA-based stochastic neural networks-implementation,” Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp. 189–198, 1994.
[3] K. Wawryn and B. Strzeszewski, ”Low power VLSI neuron cells for artificial
neural networks,” Proc. IEEE Int. Symp. on Circuits and Systems, pp. 372–375, 1996.
[4] R. Douglas et al., ”Neuromorphic analogue VLSI,” Annu. Rev. Neurosci., pp. 255–281, 1995.
[5] A. A. Cohen, ”Addressing architecture for brain-like massively parallel computers,” Proc. IEEE Euromicro Symp. on Digital System Design, pp. 594–597, 2004.
[6] L. O. Chua, ”Memristor-missing circuit element,” IEEE Trans. Circuit Theory, pp. 507–519, 1971.
[7] K.-H. Kim, ”A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications,” Nano Lett., vol. 12, pp. 389–395, 2012.
[8] A. Raghuvanshi and M. Perkowski, ”Logic synthesis and a generalized notation for memristor-realized material implication gates,” Proc. IEEE/ACM Int. Conf. on Comput.-Aided Des., pp. 470–477, 2014.
[9] R. Preissl et al., ”Compass: A scalable simulator for an architecture for cognitive computing,” Proc. IEEE Intl. Conf. on High Performance Computing, Networking, Storage and Analysis, pp. 54, 2012.
[10] B. Liu et al., ”The circuit realization of a neuromorphic computing system with memristor-based synapse design,” Neural Information Processing, pp. 357–365, 2012.
[11] W.Wen et al., ”An EDA framework for large scale hybrid neuromorphic computing systems,” Proc. ACM/IEEE Design Autom. Conf., No. 12, 2015.
[12] R. Waser et al, ”Redox-based resistive switching memories—nanoionic mechanisms, prospects, and challenges,” Adv. Mater., vol. 21, pp. 2632–2663, 2009.
[13] C. E. Merkel and D. Kudithipudi, ”Towards thermal profiling in CMOS/Memristor hybrid RRAM architectures,” Proc. IEEE Int. Conf. VLSI Design, pp. 167–172, 2012.
[14] D. Niu et al., ”Low-power dual-element memristor based memory design,” Proc. ACM/IEEE Symp. Low-Power Electronics and Design, pp. 25–30, 2010.
[15] M. Forouzanfar et al, ”Comparison of feed-forward neural network training algorithms for oscillometric blood pressure estimation,” Proc. IEEE Int. Workshop on Soft Computing Applications, pp. 119–123, 2010.
[16] J. Wu et al, ”A novel nonparametric regression ensemble for rainfall forecasting using particle swarm optimization technique coupled with artificial neural network,” Advances in Neural Networks, pp. 49–58, 2009.
[17] B. Govoreanu et al, ”10 10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation,” Tech. Dig. Int. Electron Device Meeting, pp. 729–732, 2011.
[18] A. J. Lohn1 et al, ”Analytical estimations for thermal crosstalk, retention, and scaling limits in filamentary resistive memory,” J. Appl. Phys. 115, 234507, 2014.
[19] D. Ciresan et al., ”Multi-column deep neural networks for image classification,” Proc. IEEE Computer Vision and Pattern Recognition, pp. 3642–3649, 2012.
[20] ”IEEE Standard for Information technology–Telecommunications and information exchange between systems Local and metropolitan area networks–Specific requirements Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications,” IEEE Std 802.11-2012, pp. 1–2793, 2012.
[21] M.-K. Hsu et al., ”TSV-aware analytical placement for 3D IC designs,” Proc. ACM/IEEE Design Autom. Conf., pp. 664–659, 2011.
[22] S. Chou et al., ”Structure-aware placement for datapath-intensive circuit designs,” Proc. ACM/IEEE Design Autom. Conf., pp. 762–767, 2012.
[23] R. K. Ahuja et al., Network Flows: Theory, Algorithms, and Applications, 1st ed. Prentice Hall, 1993.
[24] S. Chou et al., ”NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Trans.Comput.-Aided Design Integr. Circuits Syst., pp. 1228–1240, 2008.
[25] C. Lee and N. J. Whippany, ”An algorithm for path connections and its applications,” IRE Trans. on Elctronic Computers, pp. 346–365, 2009.
[26] Y. Zhang et al., ”FastRoute3.0: A fast and high quality global router based on virtual capacity,” Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 344–349, 2008.
[27] M. Pan and C. Chu, ”FastRoute: A step to integrate global routing into placement,” Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 464–471, 2006.
[28] U. V. Luxburg, ”A tutorial on spectral clustering,” Statistics and computing, vol. 17, pp. 395–416, 2007.
[29] J. Shi and J. Malik, ”Normalized cuts and image segmentation,” IEEE Trans. on Pattern Analysis and Machine Intelligence, vol. 22, pp. 888–905, 2000.
[30] J. J. Hopfield, ”Neural networks and physical systems with emergent collective computational abilities,” Proc. of the National Academy of Sciences of the USA, vol. 79 no. 8 pp. 2554–2558, 1982.
[31] J. Liang and H. S. Wong, ”Cross-point memory array without cell selectors—device characteristics and data storage pattern dependencies,” IEEE Trans. on Electron Devices, vol. 57, pp. 2531–2538, 2010.