本研究探討應用於FOCoS (Fan-Out Chip on Substrate)封裝內之新型銅導通孔電遷移可靠度並進行失效分析，同時研究Sn-1.8Ag銲錫接點之電遷移行為。將測試元件分別於環境溫度180oC、160oC及140oC通以0.9 A電流(換算銅導通孔之電流密度約為5.1×10^5 A/cm2；相對於銲錫接點，電流密度則約為1.6×10^4 A/cm2)後，觀察隨通電時間變化之銅導通孔與銲錫接點微結構。實驗結果顯示，Stack-via接點於180oC通電2550小時發生開路失效並呈現ˇ崩落之形貌，顯示該接點於長時間通電後，受自身結構所承受電流擁擠效應與銅導通孔及銅重佈線路層生成Cu-Sn IMC影響，內部將積累大量焦耳熱而導致接點熔融；Stagger-via接點則於180 oC通電2623小時於銅佈線路層與銅導通孔連接處發生開路失效，此被歸因於Cu-Sn IMC大量生成於銅佈線路層，體積收縮所生成的孔洞與裂縫隨電遷移效應擴大所致。本研究並探討近銅導通孔側之鎳金屬鍍層隨電遷移之消耗行為，估算其活化能於Stack-via及Stagger-via內分別為0.58 eV與0.62 eV，說明Stagger-via接點內鎳鍍層具較佳電遷移抗性與較慢的消耗速率，而為Stagger-via接點提供了更久的電遷移壽命。本研究亦觀察Sn-1.8Ag內介金屬化合物之電遷移行為，發現隨陰極端鎳層因電遷移效應逐漸消耗完畢，銲錫接點內將發生(Ni,Cu)3Sn4轉變為(Cu,Ni)6Sn5，而於電遷移下隨通電時間呈線性成長，成長機制為反應控制。

With ever-growing demands of high-performance computing ability and multifunction in much smaller electronic devices, Cu via technology has been developed as interconnects for connecting Cu redistribution lines (RDLs) to achieve high-density packaging requirements. The Cu novel Stack-/Stagger-via interconnects composed of 3 vias applying to advanced Fan-Out Chip on Substrate (FOCoS) packaging were presented and studied in this article to evaluate the electromigration (EM) reliability and explore the failure mechanism in terms of microstructure evolutions. The EM experiments were conducted at 0.9 A (approximately 5.1×105 A/cm2 for Cu vias and 1.6×104 A/cm2 for solder bumps in current density) under ambient 180oC, 160oC and 140oC. The field-emission scanning electron microscope (FESEM) microstructure evolutions suggested that the EM induced open-failure occurred at 2550 hours in Stack-via interconnects while 2623 hours in Stagger-via interconnects. For Stack-via interconnects, the open-failure showed a melting morphology such as arc-shaped notch and tiny round voids induced by resolidification of Cu as a result of severe local Joule heating giving rise to the Cu-Sn IMC transformation in Cu interconnects and current crowding effect. For Stagger-via interconnects, the open-failure between via#3 and Cu RDL resulted from voids formation caused by the Cu-Sn IMCs volume shrinkage. However, the Cu via showed an insignificant change with further stressing time, implying good EM resistance of Cu vias and suggesting Ni depletion behaviors were crucial issues in charge of the EM reliability of Cu interconnects. The activation energy calculated as the depletion of Ni UBM under EM were 0.58 eV and 0.62 eV for Stack-via and Stagger-via respectively, indicating a better EM reliability of Ni UBM in Stagger-via interconnects. The EM behavior of Sn-1.8Ag was also investigated that original (Ni,Cu)3Sn4 would transform to (Cu,Ni)6Sn5 with stressing time increasing. The growth of (Cu,Ni)6Sn5 was dominated by reaction-control, revealing that electron wind force enhanced the diffusion of Cu atoms effectively.

1. D. P. Seraphim, R. C. Lasky, and C. Y. Li, Principles of Electronic Packaging. McGraw-Hill, pp. 2-4, 1989.

2. M. G. Pecht, R. Agarwal, P. McCluskey, T. Dishongh, S. Javadpour and R. Mahajan, Electronic packaging: materials and their properties. CRC press, pp. 1-18, 2017.

3. H. D. Chang, D. Chang, K. Liu, H. S. Hsu, R. F. Tai, H. C. Huang, Y. C. Lai, C. L. Lu, C. T. Lin and S. Chiu, “Development and characterization of new generation panel fan-out (P-FO) packaging technology,” 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), pp. 947-951, 2014.

4. H. C. Cheng, K. N. Chiang, and M. H. Lee, “An Alternative Local/Global Finit e Element Approach for Ball Grid Array Typed Packages,” ASME Transaction, Journal of Electronic Packaging, vol. 120, pp.129-134, 1998.

5. I. Szendiuch, “Development in electronic packaging–moving to 3D system configuration,” Radioengineering, vol. 20, no. 1, pp. 214-220, 2011.

6. F. Appiah, “On Single Chip Package for Dual-In Integrated Circuit Packages Called Marriage IC With Switch Tests Simulation,” EasyChair, pp. 1-6, 2021.

7. N. Chen, K. Chiang, T. D. Her, Y. L. Lai and C. Chen, “Electrical characterization and structure investigation of quad flat non-lead package for RFIC applications,” Solid-State Electronics, vol. 47, no. 2, pp. 315-322, 2003.

8. D. C. Li, C. W. Yeh, C. C. Chen and H. T. Shih, “Using a diffusion wavelet neural network for short-term time series learning in the wafer level chip scale package process,” Journal of Intelligent Manufacturing, vol. 27, no. 6, pp. 1261–1272, 2016.

9. X. Fan, “Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration,” 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), pp. 1-7, 2010.

10. K. T. Chang, C. Y. Huang, H. C. Kuo, M. F. Jhong, T. L. Hsieh, M. C. Hung and C. C. Wang, “Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity,” 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp. 41-46, 2019.

11. Y. T., Lin, W. H. Lai, C. L. Kao, J. W. Lou, P. F. Yang, C. Y. Wang, and C. A. Hseih, “Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 13-18, 2016.

12. Y. Ning, Reliability of Copper-Filled Stacked Microvias in High Density Interconnect Circuit Boards. Diss. University of Maryland, College Park, pp. 6-7, 2017.

13. C. K. Hu and J. M. E. Harper, “Copper interconnections and reliability." Materials Chemistry and Physics,” vol. 52, no. 1, pp. 5-16, 1998.

14. S. Spiesshoefer, J. Patel, T. Lam, L. Cai, S. Polamreddy, R. F. Figueroa, S. L. Burkett, L. Schaper, R. Geil and B. Rogers, “Copper electroplating to fill blind vias for three-dimensional integration,” Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 24, no. 4, pp. 1277-1282, 2006.

15. F. Liu, G. E. White, V. Sundaram, A. O. Aggarwal, S. M. Hosseini, D. Sutter and R. R. Tummala, “A novel technology for stacking microvias on printed wiring board,” 53rd Electronic Components and Technology Conference, 2003. Proceedings., pp. 1134-1139, 2003.

16. K. Kalayeh, N. Hernandez, C. Hillman and N. Blattau, “Automated Method Using Finite Element Simulation to Identify Microvia Stacks at Risk of Separation in Complex PCB Designs,” 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp. 1-4, 2019.

17. W. W. Shen, and K. N. Chen, “Three-dimensional integrated circuit (3D IC) key technology: through-silicon via (TSV),” Nanoscale research letters, vol. 12, no. 1, pp. 1-9, 2017.

18. J. Kim, J. S. Pak, J. Cho, E. Son, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M. S. Suh, K. Y. Byun and J. Kim, “High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV),” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 181-195, 2011.

19. W. W. Shen, and K. N. Chen, “Three-dimensional integrated circuit (3D IC) key technology: through-silicon via (TSV),” Nanoscale research letters, vol. 12, no. 1, pp. 1-9, 2017.

20. I. Shohji, T. Yoshida, T. Takahashi and S. Hioki, “Comparison of low-melting lead-free solders in tensile properties with Sn–Pb eutectic solder,” Journal of Materials Science: Materials in Electronics, vol. 15, no. 4, pp. 219–223, 2004.

21. M. Abtew and G. Selvaduray, “Lead-free solders in microelectronics,” Materials Science and Engineering: R: Reports, vol. 27, no. 5-6, pp. 95-141, 2000.

22. K. Suganuma, S. J. Kim and K. S. Kim, “High-temperature lead-free solders: Properties and possibilities,” Journal of the Minerals, Metals and Materials Society, vol. 61, no. 1, pp. 64-71, 2009.

23. K. Suganuma, “Advances in lead-free electronics soldering,” Current Opinion in Solid State and Materials Science, vol. 5, no. 1, pp. 55-64, 2001.

24. M. S. Alam, M. Basit, J. C. Suhling and P. Lall, “Mechanical characterization of SAC305 lead free solder at high temperatures,” 2016 15th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), pp. 755-760, 2016.

25. J. Helneder, C. Hoyler, M. Schneegans and H. Torwesten, “Evaluation of lead-free SnAg solder ball deposition and reflow processes for flip chip applications,” Microelectron. Engineering, vol. 82, no. 3-4, pp. 581-586, 2005.

26. S. Arai, H. Akatsuka and N. Kaneko, “Sn–Ag solder bump formation for flip-chip bonding by electroplating,” Journal of The Electrochemical Society, vol. 150, no. 10, pp. C730-C734, 2003.

27. K. Suganuma, S. H. Huh, K. Kim, H. Nakase, Y. Nakamura, “Effect of Ag Content on Properties of Sn-Ag Binary Alloy Solder,” Materials Transactions, vol. 42, no. 2, pp. 286-291, 2001.

28. R. S. C. Vargas and V. Gonda, “Comparison of the thermal-mechanical behavior of a soldered stack influenced by the choice of the solder,” 2019 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp. 1-6, 2019.

29. N. C. Lee, Lead-free soldering-where the world is going. Society of Manufacturing Engineers, 2000.

30. J. H. Lau, “Flip chip technology versus fowlp,” Fan-Out Wafer-Level Packaging, Springer, Singapore, pp. 21-68, 2018.

31. 林建泰、林光隆，「覆晶接合銲錫隆點之製程及以真空技術製作之UBM」，真空科技，15:4卷，頁40-47，民91。

32. H. Okamoto and T.B. Massalski, Binary Alloy Phase Diagrams. William W. Scott, vol. 1, pp. 1757-1759, 1986.

33. S. Yang, C. J. Yang and F. Y. Ouyang, “Interfacial reaction of Ni3Sn4 intermetallic compound in Ni/SnAg solder/Ni system under thermomigration,” Journal of Alloys and Compounds, vol. 674, pp. 331-340, 2016.

34. A. Lis, C. Kenel and C. Leinenbach, “Characteristics of reactive Ni3Sn4 formation and growth in Ni-Sn interlayer systems,” Metallurgical and Materials Transactions A, vol. 47, no. 6, pp. 2596-2608, 2016.

35. H. Feng, J. Huang, X. Peng, Z. Lv, Y. Wang, J. Yang, S. Chen, X. Zhao, “Microstructural Evolution of Ni-Sn Transient Liquid Phase Sintering Bond during High-Temperature Aging,” Journal of Electronic Materials, vol. 47, no. 8, pp. 4642-4652, 2018.

36. H. Okamoto and T.B. Massalski, Binary Alloy Phase Diagrams, William W. Scott, vol. 1, p. 965, 1986.

37. S. W. Chen and Y. W. Yen, “Interfacial reactions in Ag-Sn/Cu couples,” Journal of Electronic Materials, vol. 28, no. 11, pp. 1203-1208, 1999.

38. S. Ahat, M. Sheng, and L. Luo, “Microstructure and shear strength evolution of SnAg/Cu surface mount solder joint during aging,” Journal of Electronic Materials, vol. 30, no. 10, pp. 1317-1322, 2001.

39. D. R. Flanders, E. G. Jacobs, R. F. Pinizzotto, “Activation energies of intermetallic growth of Sn-Ag eutectic solder on copper substrates,” Journal of Electronic Materials, vol. 26, no. 7, pp. 883–887, 1997.

40. Q. K. Zhang, W. M. Long and Z. F. Zhang, “Growth behavior of intermetallic compounds at Sn–Ag/Cu joint interfaces revealed by 3D imaging,” Journal of Alloys and Compounds, vol. 646, pp. 405-411, 2015.

41. B. Chao, S. H. Chae, X. Zhang, K. H. Lu, M. Ding, J. Im and P. S. Ho, “Electromigration enhanced intermetallic growth and void formation in Pb-free solder joints,” Journal of Applied Physics, vol. 100, no. 8, p. 084909, 2006.

42. X. Luhua and J. H. L. Pang, “Interfacial IMC and Kirkendall void on SAC solder joints subject to thermal cycling,” 2005 7th Electronic Packaging Technology Conference, p. 5, 2005.

43. C. Yu, Y. Yang, H. Lu and J. M. Chen, “Effects of Current Stressing on Formation and Evolution of Kirkendall Voids at Sn–3.5Ag/Cu Interface,” Journal of Electronic Materials, vol. 39, no. 8, pp. 1309–1314, 2010.

44. O. Mokhtari, M. S. Kim, H. Nishikawa, F. Kawashiro, S. Itoh, T. Maeda, T. Hirose and T. Eto, “Investigation of formation and growth behavior of Cu/Al intermetallic compounds during isothermal aging,” Transactions of The Japan Institute of Electronics Packaging, vol. 7, no. 1, pp. 1-7, 2014.

45. Y. Tamou, J. Li, S. W. Russell, and J. W. Mayer, “Thermal and ion beam induced thin film reactions in cu-al bilayers,” Nucl. Instrum. Methods Phys. Res. B, vol. 64, no. 1-4, pp. 130–133, 1992.

46. J. Osenbach, B. Q. Wang, S. Emerich, J. DeLucca and D. Meng, “Corrosion of the Cu/Al interface in Cu-Wire-bonded integrated circuits,” 2013 IEEE 63rd Electronic Components and Technology Conference, pp. 1574-1586, 2013.

47. J. H. L. Pang, K. H. Prakash and T. H. Low, “Isothermal and thermal cycling aging on IMC growth rate in Pb-free and Pb-based solder interfaces,” The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543), vol. 2, pp. 109-115, 2004.

48. C. Y. Liu, L. Ke, Y. C. Chuang, and S. J. Wang, “Study of electromigration-induced Cu consumption in the flip-chip Sn/Cu solder bumps,” Journal of Applied Physics, vol. 100, no. 8, p. 083702, 2006.

49. P. S. Ho and T. Kwok, “Electromigration in metals,” Reports on Progress in Physics, vol. 52, no. 3, pp. 303-352, 1989.

50. F. Skaupy, “Electrical conduction in metals,” Verband Deutscher Physikalischer Gesellschaften, vol. 16, pp. 156-157, 1914.

51. V. B. Fiks, “Interaction of conduction electrons with single dislocations in metals,” Phys. Solid State, vol. 1, p. 14, 1959.

52. H. B. Huntington and A. R. Grone, “Current-induced marker motion in gold wires,” Journal of Physics and Chemistry of Solids, vol. 20, no. 1-2, pp. 76-87, 1961.

53. C. Y. Hsu, D. J. Yao, S. W. Liang, C. Chen and E. C. Yeh, “Temperature and current-density distributions in flip-chip solder joints with Cu traces,” Journal of electronic materials, vol. 35, no. 5, pp. 947-953, 2006.

54. M. AbdelAziz and M. Mayer, “In-situ Determination of Specimen Temperature during Electromigration Testing of Solder Joint,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). IEEE, pp. 1767-1772, 2021.

55. C. E. Ho, C. H. Yang, and L. H. Hsu., “Electromigration in thin-film solder joints,” Surface and Coatings Technology, vol. 259, pp. 257-261, 2014.

56. Y. R. Kim, H. Madanipour, A. T. Osmanson, M. Tajedini, C. U. Kim, P. F. Thompson and Q. Chen, “Relationship Between the Grain Orientation and the Electromigration Reliability of Electronic Packaging Interconnects,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 2334-2339, 2021.

57. D. Yang and Y. C. Chan, “The characteristics of electromigration and thermomigration in flip chip solder joints,” 2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC), pp. 43-47, 2007.

58. M. Lu, D. Y. Shih, P. Lauro, C. Goldsmith and D. W. Henderson, “Effect of Sn grain orientation on electromigration degradation mechanism in high Sn-based Pb-free solders,” Applied physics letters, vol. 92, no. 21, p. 211909, 2008.

59. K. N. Tu, “Recent advances on electromigration in very-large-scale-integration of interconnects,” Journal of applied physics, vol. 94, no. 9, pp. 5451-5473, 2003.

60. R. Darveaux, J. D. V. Hoang and B. Vijayakumar, “Electromigration performance of WLCSP solder joints,” SMTA International 2014 Proceedings, 2014.

61. J. W. Nah, J. O. Suh and K. N. Tu., "Effect of current crowding and Joule heating on electromigration-induced failure in flip chip composite solder joints tested at room temperature,” Journal of applied physics, vol. 98, no. 1, p. 013715, 2005.

62. S. W. Liang, Y. W. Chang and C. Chen, “Effect of Al-trace dimension on Joule heating and current crowding in flip-chip solder joints under accelerated electromigration,” Applied physics letters, vol. 88, no. 17, p. 172108, 2006.

63. Y. Wang and Y. Yao, “A theoretical analysis to current exponent variation regularity and electromigration-induced failure,” Journal of Applied Physics, vol. 121, no .6, p. 065701, 2017.

64. A. S. Oates, “Current density dependence of electromigration failure of submicron width, multilayer Al alloy conductors,” Applied physics letters, vol. 66, no. 12, pp. 1475-1477, 1995.

65. S. H. Chae, X. Zhang, H. L. Chao, K. H. Lu, P. S. Ho, M. Ding, P. Su, T. Uehling and L. N. Ramanathan, “Electromigration lifetime statistics for Pb-free solder joints with Cu and Ni UBM in plastic flip-chip packages,” 56th Electronic Components and Technology Conference 2006, pp. 7-8, 2006.

66. J. Lienig and M. Thiele, Fundamentals of Electromigration-Aware Integrated Circuit Design. Berlin: Springer, pp. 13-14, 2018.

67. 陳厚光、張立，「掃描式電子顯微鏡中之背向電子繞射分析技術」，科儀新知，卷152，頁22-30，2006。

68. Z. Zhang, X. Duan, B. Qiu, Z. Yang, D. Cai, P. He, D. Jia and Y. Zhou, “Preparation and anisotropic properties of textured structural ceramics: A review,” Journal of Advanced Ceramics, vol. 8, no. 3, pp. 289-332, 2019.

69. L. U. O. Hu, J. I. N. G. Ran, Y. M. Cui, H. L. Wang, and R. M. Wang, “Improvement of fabrication precision of focused ion beam by introducing simultaneous electron beam,” Progress in Natural Science: Materials International, vol. 20, pp. 111-115, 2010.

70. M. M. Waldrop, “More than moore,” Nature, vol. 530, no. 7589, pp. 144-148, 2016.

71. R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P.P. Pande, C. Grecu, A. Ivanov, “System-on-Chip: Reuse and Integration,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1050-1069, 2006.

72. N. Rangarajan, S. Patnaik, J. Knechtel, S. Rakheja and O. Sinanoglu, “Heterogeneous 2.5 D and 3D Integration for Securing Hardware and Data,” The Next Era in Hardware Security, Springer, Cham, pp. 123-194, 2021.

73. H. B. Huntington, “Diffusion in Solids : Recent Developments,” edited by A. S. Nowick and J. J. Burton, Academic Press, New York, pp. 303-352, 1975.

74. G. Y. Jang, C. S. Huang, L. Y. Hsiao, J. G. Duh and H. Takahashi, “Mechanism of interfacial reaction for the Sn-Pb solder bump with Ni/Cu under-bump metallization in flip-chip technology,” Journal of electronic materials, vol. 33, no. 10, pp. 1118-1129, 2004.

75. F. Gao and J. Qu, “Elastic moduli of (Ni,Cu)3Sn4 ternary alloys from first-principles calculations,” Journal of electronic materials, vol. 39, no. 11, pp. 2429-2434, 2010.

76. H. Gan and K. N. Tu, “Polarity effect of electromigration on kinetics of intermetallic compound formation in Pb-free solder V-groove samples,” Journal of applied physics, vol. 97, no. 6, p. 063514, 2005.

77. J. Y. Juang, S. T. Lu, C. J. Zhan, C. Su-Ching, C. W. Fan, J. S. Peng and T. H. Chen, “Development of 30 μm pitch Cu/Ni/SnAg micro-bump-bonded chip-on-chip (COC) interconnects,” 2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, pp. 1-4, 2010.

78. F. Y. Ouyang, H. Hsu, Y. P. Su and T. C. Chang, “Electromigration induced failure on lead-free micro bumps in three-dimensional integrated circuits packaging,” Journal of Applied Physics, vol. 112, no. 2, p. 023505, 2012.

79. Y. C. Chu, C. J. Zhan, H. W. Lin, Y. W. Huang and C. Chen, “Electromigration in microbumps with Cu-Sn intermetallic compounds,” 2016 International Conference on Electronics Packaging (ICEP), pp. 252-255, 2016.

80. C. C. Li, C. K. Chung, W. L. Shih and C. R. Kao, “Volume shrinkage induced by interfacial reaction in micro-Ni/Sn/Ni joints,” Metallurgical and Materials Transactions A, vol. 45, pp. 2343-2346, 2014.

81. C. L. Liang, K. L. Lin and P. J. Cheng, “Effect of Au/Pd bilayer metallization on solder/Cu interfacial reaction and growth kinetics of CuSn intermetallic compounds during solid-state aging,” Surface and Coatings Technology, vol. 319, pp. 55-60, 2017.

82. Y. Wang, S. Chae, J. Im and P. S. Ho, “Kinetic study of intermetallic growth and its reliability implications in Pb-free Sn-based microbumps in 3D integration,” 2013 IEEE 63rd Electronic Components and Technology Conference, pp. 1953-1958, 2013.

83. J. Xiong, Y. Peng, H. Zhang, J. Li and F. Zhang, “Microstructure and mechanical properties of Al-Cu joints diffusion-bonded with Ni or Ag interlayer,” Vacuum, vol. 147, pp. 187-193, 2018.

84. S. W. Liang, S. H. Chiu and C. Chen., “Effect of Al-trace degradation on Joule heating during electromigration in flip-chip solder joints,” Applied physics letters, vol. 90, no. 8, p. 082103, 2007.

85. C. L. Liang, Y. S. Lin, C. L. Kao, D. Tarng, S. B. Wang, Y. C. Hung and K. L. Lin, “Electromigration failure study of a fine-pitch 2μm/2μm L/S Cu redistribution line embedded in polyimide for advanced high-density fan-out packaging,” 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). IEEE, pp. 361-366, 2020.

86. J. Xu, S. McCann, H. Wang, J. Wang, V. Pham, S. R. Cain, G. Refai-Ahmed and S. B. Park, “An assessment of electromigration in 2.5 D packaging,” 2019 IEEE 69th Electronic Components and Technology Conference (ECTC). IEEE, pp. 2150-2155, 2019.

87. Y. S. Lai and C. L. Kao, “Characteristics of current crowding in flip-chip solder bumps,” Microelectronics Reliability, vol. 46, no. 5–6, pp. 915-922, 2006.

88. S. A. Belyakov and C. M. Gourlay, “NiSn4 formation during the solidification of Sn–Ni alloys,” Intermetallics, vol. 25, pp. 48-59, 2012.

89. R. Kubiak and M. Wołcyrz, “X-ray investigations of crystallization and thermal expansion of AuSn4, PdSn4 and PtSn4,” Journal of the Less Common Metals, vol. 109, no. 2, pp. 339-344. 1985.

90. B. Chao, S. H. Chae, X. Zhang, K. H. Lu, M. Ding, J. Im and P. S. Ho, “Investigation of diffusion and electromigration parameters for Cu–Sn intermetallic compounds in Pb-free solders using simulated annealing,” Acta Materialia, vol. 55, pp. 2805-2814, 2007.

91. J. W. Jang, L. N. Ramanathan and D. R. Frear, “Electromigration behavior of lead-free solder flip chip bumps on NiP/Cu metallization,” Journal of Applied Physics, vol. 103, no. 12, p. 123506, 2008.

92. P. Liu, A. Overson and D. Goyal, “Electromigration induced interfacial microstructure evolution of solder joints in electronic packaging,” 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), pp. 473-478, 2020.

93. J. Y. Wang, Y. K. Tang, C. Y. Yeh, P. J. Chang, Y. X. Lin, E. J. Lin, C. Y. Wu, W. X. Zhuang and C. Y. Liu, “Kinetics of Ni solid-state dissolution in Sn and Sn3.5Ag alloys,” Journal of Alloys and Compounds, vol. 797, pp. 684-691, 2019.

94. M. Lu, D. Y. Shih, C. Goldsmith and T. Wassick, “Comparison of electromigration behaviors of SnAg and SnCu solders,” 2009 IEEE International Reliability Physics Symposium, pp. 149-154, 2009.

95. Y. R. Kim, H. Madanipour, A. T. Osmanson, M. Tajedini, C. U. Kim, P. F. Thompson and Q. Chen, “Relationship Between the Grain Orientation and the Electromigration Reliability of Electronic Packaging Interconnects,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 2334-2339, 2021.

96. B. U. Hwang, K. D. Min, C. J. Lee, J. H. Kim and S. B. Jung, “Pressureless transient liquid phase bonding using SAC305 with hybrid Ag particles and its reliability under high-temperature storage test,” Materialia, vol. 12, p. 100808, 2020.

97. J. Zhang, B. H. Wang, G. H. Chen, R. M. Wang, C. H. Miao, Z. X. Zheng and W. M. Tang, “Formation and growth of Cu–Al IMCs and their effect on electrical property of electroplated Cu/Al laminar composites,” Transactions of Nonferrous Metals Society of China, vol. 26, no. 12, pp. 3283-3291. 2016.

98. M. He, Z. Chen and G. Qi, “Mechanical strength of thermally aged Sn-3.5 Ag/Ni-P solder joints,” Metallurgical and Materials Transactions A, vol. 36, no. 1, pp. 65-75, 2005.

99. Y. Liu, M. Li, M. Jiang, D. W. Kim, S. Gu and K. N. Tu, “Joule heating enhanced electromigration failure in redistribution layer in 2.5 D IC,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 1359-1363, 2016.

100. K. S. Kim, S. H. Huh and K. Suganuma, “Effects of cooling speed on microstructure and tensile properties of Sn–Ag–Cu alloys,” Materials Science and Engineering: A, vol. 333, no. 1-2, pp. 106-114, 2002.

101. Y. Xia, X. Xie, C. Lu and J. Chang, “Coupling effects at Cu (Ni)–SnAgCu–Cu (Ni) sandwich solder joint during isothermal aging” Journal of Alloys and compounds, vol. 417, no. 1-2, pp. 143-149, 2006.