在AC掃描延遲測試的環境中，擷取測試結果(capture test responses)的瞬間可能會導致電路產生極大的電流需求及功率消耗，進而發生電壓下降(IR-drop)的現象，這個現象可能會造成測試失敗及良率的損失。近年來，有數個方法藉由修改測試向量(test pattern)，以減少電路切換動作(switching activity)來解決因過大功率消耗而產生的電壓下降問題。然而，這些方法所產生的測試向量仍然可能使電路進入非正常性運作的模式(nonfunctional state)，此模式會產生大量的電路切換動作。因此，在此研究裡，我們提出一個高效率測試向量決定方法，以產生確保安全擷取功率(capture power safety)，其包含了兩個演算法：測試向量修改 (test pattern refinement)及低功率測試向量產生(low-power test generation)演算法。有別於直接修改測試向量以降低電路切換動作的方法，我們的方法丟棄了高擷取功率的測試向量，轉而去修改低擷取功率的測試向量，以偵測因丟棄測試向量而不能被測得的錯誤(faults)。若經過測試向量修改演算法後，仍然有尚未被測到的錯誤，則低功率測試向量產生演算法會針對這些錯誤產生新的低功率測試向量。據筆者所知，這是第一個提出藉由修改低擷取功率測試向量，來解決擷取功率消耗過大的問題。實驗結果顯示，在ISCAS’89及ITC’99電路中，經由修改低擷取功率測試向量平均再多測到75% 的錯誤。 更重要的是，在不同的功耗消耗限制下，我們的方法可以平均減少 7.96-12.76% 的測試資料量且沒有錯誤覆蓋率(fault coverage)損失。

The power required to capture test responses during AC scan-based tests may be excessive, and the resulting large power dissipation can lead to a significant current demand that may cause the IR-drop problem and induce unnecessary yield loss. Many methods have been proposed to address this by reducing the switching activities of patterns. However, these methods cannot eliminate all power issues, because some patterns may still cause the circuit to enter a nonfunctional state and generate significant circuit switching activities. This paper presents an efficient test pattern determination method for capture power safety. The proposed method includes two processes: test pattern refinement and low-power test generation. Instead of reducing the switching activity of power-risky patterns, the power-risky patterns are discarded to ensure capture power safety, and test pattern refinement process is used to refine the power-safe patterns to detect the faults that were originally only detected by the power-risky patterns. If some faults still remain undetected, low-power test generation is used to generate power-safe patterns in order to detect them. To the best of the author’s knowledge, this is the first method that refines the power-safe patterns to address the capture power problem. The experimental results on ISCAS’89 and ITC’99 benchmark circuits show that an average of 75% of the faults which originally only detected by power-risky patterns can be detected by refining power-safe patterns. Furthermore, the required test data volume can be reduced by 7.96-12.76% on average without fault coverage loss under different power constraints.

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