簡易檢索 / 詳目顯示

研究生: 方嘉鋒
Fang, Jia-Feng
論文名稱: 相位移及光學近階修正技術應用在單一光罩雙鑲嵌製程之研究
Application of Phase Shift and Optic Proximity Correction Technology for Single Mask Dual Damascene Process
指導教授: 彭洞清
Perng, Dung-Ching
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 56
中文關鍵詞: 微影雙鑲嵌相位移光罩光學近階修正
外文關鍵詞: mask, optic proximity correction, phase shift, prolith, dual damascene, lithography
相關次數: 點閱:104下載:6
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 雙鑲嵌(Dual Damascene)製程結構已廣泛用於銅金屬連線,而製作方式有很多種,目前最常用的有中介窗優先(via first)、溝漕優先(Trench first)以及內嵌硬質罩幕(Buried hard mask),然而不論使用哪種方式製作常常會用到蝕刻中止層或硬質罩幕層搭配低介電(low k)材料使得整個製程複雜。不管用何種方法製作雙鑲嵌結構,都需要兩面光罩及兩次曝光程序,在現今先進製程的光罩一面需要兩百萬元,而ㄧ層金屬層就需要兩面光罩將增加晶片製造成本。隨著晶片尺寸的縮小,也增加了中介窗與溝漕的對準誤差(misalignment)導致微影失敗而需要重新微影。隨著金屬層數的增加,以上問題的更增加了製程花費,也降低了生產速度與良率。
      本論文主要是研發ㄧ特殊相位移光罩,在一片光罩上同時含有中介窗(via)與溝漕(trench)圖樣,為了達到一次曝光能形成雙鑲嵌結構在光阻上,我們將中介窗與溝漕光罩合併並設計使此合併後的光罩有不同的能量穿透。在溝漕部分我們以斑馬紋(Zebra)的相位差光柵結構使光產生破壞性干涉造成能量減少達到部分曝光,中介窗的部份以全透光方式處理,而此研究主要以KLA-Tencor公司的Prolith v.9.2模擬軟體來進行。
    本論文中,中介窗與溝漕合併後之單一光罩具有0.51μm的聚焦深度以及6%曝光寬容度,而穿透溝槽區之光強度可藉由調整光柵相位而得,相位度數將影響穿透能量,而中介窗與溝漕間之對比度可藉由改變光柵寬度來調整,在光柵寬度小於光學解析度下,越小的寬度將造成中介窗與溝漕處有較高的對比度。為了符合實際電路設計需求,具轉折處之溝槽也能製作出來但需要更進階之光學修正。為了獲得製程可行之聚焦深度(depth of focus, DOF)、線寬(critical dimension, CD)、數值孔徑(numerical aperture, NA)與光源相擾(sigma, σ),本論也使用光學近階修正(optic proximity correction, OPC)技術尋求最佳化製程。
    我們可以藉此單一光罩取代傳統兩面光罩來製作雙鑲嵌結構,降低光罩數及光罩成本,而在製程上也僅需ㄧ次微影、蝕刻、灰化及清洗,大大降低生產成本且簡化製程並降低對準誤差問題。

    Dual damascene process has been used for copper interconnect. There are many schemes to fabricate dual damascene structure. The most common integration approaches for the dual damascene architecture are via first, trench first and buried hard mask. Which mask first, using etch stop and hard masks or not and the use of ultra low k materials in advanced interconnect make dual damascene process very complicated.
    No matter which dual damascene scheme used all of them need two masks and two lithography processes. One advanced mask cost about two million NT$ and one metal layer needs two masks. With the increasing trend of metal layers of modern IC, the mask cost will add additional burden on already high manufacture cost. With rapidly decreasing chip feature size, the misalignment tolerance is not that far from critical dimension (CD). The existence of misalignment between via and trench mask will cause more rework on lithography steps. The increases of metal layers and higher rework rate on high cost lithography steps can only make things worse. Misalignment will also degrade the process and product yield. It is also a reliability killer.
    This thesis is to develop novel lithography process to fabricate dual damascene structure just one mask. The unique mask combines via and trench pattern layout. To achieve one exposure having dual damascene shape on photoresist, we need different exposure energy settings or conditions at via and trench areas at the same time. This thesis used phase shift and optic interference technique to weaken the exposure energy on trench to obtain partial exposure. Zebra pattern phase shifted gratings on trench area were used to achieve destructive interference. Via area is clear (no Cr for positive resist) to obtain full exposure. The thesis used KLA-Tencor’s Prolith v.9.2 to simulate the lithographic processes using the combined mask structure.
    The combined mask has DOF of 0.51μm and 6% exposure latitude for via and trench overlap process window. The light intensity pass through trench area can be adjusted by changing the grating phase. Degree of shifted phase will affects the transmission energy which influences image contrast. The contrast between via and trench can be modified by adjusting grating width. For grating width less than the optical resolution, smaller grating width has better contrast on relative intensity between via and trench. In order to fulfill the design rule, trench pattern with turning corner was also simulated. Trench turning area needs aggressive optical proximity correction. To obtain preferred workable process like depth of focus, target CD, numerical aperture and sigma, optical proximity correction technique was used.
    By using this unique single mask instead of two traditional masks, we can fabricate dual damascene structure. This cut the high mask cost in half. With one mask, we need only one lithography step, one etch, one ash and one clean instead of two each. It saves process cost significantly, simplifies the complicated dual damascene process and completely removed two masks’ misalignment problems. It will also boost yield and improves product reliability.

    Chinese abstract English abstract Contents Table Captions Figure Captions Chapter 1 Introduction 1.1 Interconnect dual damascene processes…………………………...1 1.2 Lithography and resolution enhancement techniques…………….12 1.3 Background and objective of the thesis…………………………21 Chapter 2 Concept of single mask dual damascene process 2.1 Single mask dual damascene process……………………………..25 2.2 Mask design…………………………………………………..……….27 2.3 Simulation procedures………………………………………………..32 Chapter 3 Result and discussions 3.1 Optical parameters selections……………………………………….36 3.2 Single mask simulation methodology……………………………….39 3.3 Trench with phase shifted grating……………………………………41 3.4 Simulation of the combined mask……………………………………46 Chapter 4 Conclusions and Future Work 4.1 Conclusions……………………………………………...…………….53 4.2 Future work…………………………………………………………….55 References

    [1] Xuelong Shi,Allen Fung, Stephen Hsu, Zongyu Li, Tim Nguyen, Robert Socha, Will Conley, Mircea Dusa, "Dual damascene photo process using negative tone resist", Proceedings of SPIE
    Vol.3999 (2000)
    [2] Mark T. Bohr, "Interconnect scaling-the real limiter to high performance ULSI", IEEE IEDM, 10-13 DEC. pp.241-244 (1995)
    [3]Burn J. Lin, “The k3 coefficient in nonparaxial λ/NA scaling equations for resolution, depth of focus, and immersion lithography”, Society of Photo-Optical Instrumentation Engineers, pp.7-12 (2002)
    [4]Ban P. Wang, Anurag Mittal, Yu Cao, Greg Starr, “Nano-CMOS circuit and physical design”, John Wiley & Sons Inc. US. (2004)
    [5]Bruce W. Smith, “Mutual optimization of resolution enhancement techniques”, J. Microlith Microfabrication, Microsyst. 1, 95 (2002)
    [6]Yong-Ho Oh, Jai-Cheol Lee, and Sungwoo Lim ” Resolution enhancement through optical proximity correction and stepper parameter optimization for 0.12-μm mask pattern” Proc. SPIE Int.
    Soc. Opt. Eng. 3679, 607 (1999)
    [7] Puneet Gupta, Andrew B. Kahng, Swamy Muddu, Sam Nakagawa, Chul-Hong Park, “Modeling OPC complexity for design for manufacturability”, Proc. SPIE Vol.5992, p. 612-622, 25th Annual BACUS Symposium on Photomask Technology; J. Tracy Weed,
    Patrick M. Martin; Eds. (Nov 2005)
    [8]Emiko Sugiura, Hisashi Watanabe, Tadashi Imoriya, Yoshihiro Todokoro, “Fabrication and pattern transfer of optical proximity correction(OPC) mask”, SPIE Vol.2254 Photomask and X-Ray Mask
    Technology, pp.183-192 (1994)
    [9] Eric S. Wu, Balu Santhanam, and S. R. J. Brueck, “General framework for 36 parameter optimization in imaging interferometric lithography”, J. Microlith Microfabrication, Microsyst. 4, 023009
    (2005)
    [10]Marc D. Levenson, N. S. Viswanwthan, Eobert A. Simpson, “Improving resolution in photolithography with a phase-shifting mask”, IEEE Transactions on Electron Devices, vol. ed-29, No. 12
    pp.1828-1836 (1982)
    [11]Marc D. Levenson, “What is a phase-shifting mask?”, SPIE Vol. 1496 10th Annual Symposium on Microlithography (1990)
    [12]B. J. Lin, “Off-axis illumination – Working principles and comparison with alternating phase-shifting masks”, SPIE Vol. 1927 Optical/Laser Microlithography VI (1993)
    [13]L. Arnaud, T. Berger, G. Reimbold, “Evidence of grain-boundary versus interface diffusion in electromigration experiments in copper damascene interconnects”, Journal of Applied Physics, Vol. 93
    Issue 1, pp.192 (2003)
    [14]Stanley Wolf, “Introduction to dual damascene interconnect processes”, SILICON PROCESSING FOR THE VLSI ERA Vol. 4, pp. 674-679 Publisher: Lattice Press (2004).
    [15]P. Josh Wolf, “Overview of Dual Damascene Cu/Low-k Interconnect”, IITC workshop (2004)
    [16]Robert H. Havemann and James A. Hutchby, “High-Performance Interconnects: An Integration Overview”, PROCEEDINGS OF THE IEEE, Vol. 89, No. 5, May (2001)
    [17]Ogawa, E.T.; Ki-Don Lee; Blaschke, V.A.; Ho, P.S.,” Electromigration reliability issues in dual-damascene Cu interconnections” IEEE Transactions on Reliabilit, Volume 51,
    Issue 4, Page 403 – 419, Dec. 2002
    [18]龍文安, “半導體微影技術”, 五南圖書出版公司, 台灣, pp. 270-293 (2004)
    [19]ASML product website: http://www.asml.com/asmldotcom/show.do?ctx=6717
    [20]NIKON product website:
    http://www.ave.nikon.co.jp/pec_e/products/nsr.htm
    [21]Jos de Klerk, “Performance of a high NA, dual stage 193nm TWINSCANTM step & scan system for 80nm applications”, Optical Microlithography XVI, Anthony Yen, Editor, Proceedings of SPIE
    Vol. 5040 (2003)
    [22]ITRS Lithography (2006)

    下載圖示 校內:2008-07-06公開
    校外:2008-07-06公開
    QR CODE