近年來，隨著量子電腦與高效能運算電腦的快速發展，為支援龐大的運算需求，對於穩定且高效的低溫資料儲存技術之需求亦隨之提升。量子電腦為降低熱擾動對量子位元（qubits）穩定性的影響，必須於低溫環境中操作。
另一方面，隨著CMOS製程技術不斷微縮，靜電放電（ESD）防護電路在高密度積體電路中的重要性日益提升。傳統ESD測試與防護電路設計多以常溫條件為主，然而隨著低溫電子技術的發展，低溫環境對ESD防護電路之影響已成為不容忽視的關鍵課題。
本研究針對CMOS製程之ESD防護電路，於300K至4K溫度範圍內進行測試與分析，探討不同溫度條件下ESD防護電路之耐受度與元件行為變化，期望為低溫應用環境下之電路設計提供可靠之實驗數據與技術參考。

In recent years, with the rapid advancement of quantum computers and high-performance computing systems, the demand for stable and efficient cryogenic data storage technologies has grown to support increasingly large computational workloads. Quantum computers must operate under cryogenic conditions to minimize thermal disturbances that affect the stability of quantum bits (qubits).
At the same time, as CMOS process technology continues to scale down, the importance of electrostatic discharge (ESD) protection circuits in high-density integrated circuits has become increasingly prominent. Conventional ESD testing and protection circuit design have primarily focused on room-temperature conditions. However, with the development of cryogenic electronics, the impact of low-temperature environments on ESD protection circuits has emerged as a critical issue that can no longer be overlooked.
This study focuses on ESD protection circuits fabricated using CMOS processes, conducting testing and analysis across a temperature range from 300K down to 4K. It investigates the changes in ESD robustness and device behavior under different temperature conditions, aiming to provide reliable experimental data and technical references for circuit design intended for cryogenic applications.

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