射頻接收器前端電路中，包含了低雜訊放大器與混頻器。低雜訊放大器為接收器的第一級，用以接收訊號，加以放大並減少雜訊值，增加訊號傳輸的正確性；混頻器為第二級，接收經由低雜訊放大器放大之訊號，與本地振盪器產生之本地訊號加以混頻，產生中頻訊號輸出至後段電路中。

在本篇論文中記載數個射頻前端電路之設計，包含以下電路：3.1～10.6 GHz超寬頻折疊式混頻器、3.5 GHz WiMAX 主動式Balun 折疊式混頻器、3.5 GHz WiMAX 低雜訊放大器。

3.1～10.6 GHz超寬頻折疊式混頻器，利用並聯之LC與RLC來構成超寬頻之輸入匹配電路，達成UWB之頻寬要求與良好之轉換增益平坦度。在3～10 GHz的S11低於-10dB，轉換增益為1.7~6.6dB，P1dB與IIP3為-18dBm與-2dBm，消耗功率為10.4mW。

3.5 GHz WiMAX 主動式Balun 折疊式混頻器，應用於全球微波存取互通性通訊系統，延續上述電路主體架構，利用內建之主動式Balun將單端輸入訊號轉為混頻器所需之差動輸入訊號。針對WiMAX 3.5 GHz頻帶完成整體混頻器設計。轉換增益為6.2dB，P1dB與IIP3為-14dBm與-7dBm，消耗功率為16.8mW。

3.5 GHz WiMAX 低雜訊放大器，應用於全球微波存取互通性通訊系統，利用forward body bias方式，設計出一運作於低電壓，低消耗功率之低雜訊放大器。增益為17.6dB，P1dB與IIP3為-15dBm與-6dBm，Noise Figure為2.5dB，消耗功率為8.6mW。

本論文中之電路設計是以TSMC 0.18 μm CMOS製程之model進行模擬，並透過CIC之申請下線，完成晶片之製作。

Low noise amplifier is the first stage of the receiver. It can amplify the received signal and reduce the noise of whole system in order to improve the accuracy of transmission. Mixer is the second stage of the receiver. It will mix the signal amplified by low noise amplifier with local signal induced by voltage control oscillator and induce intermediate-frequency signal to later stages.

In this thesis, we designed some radio frequency front-end circuits, contain 3.1~10.6 GHz folded-cascode mixer, 3.5 GHz folded-cascode mixer with active balun, and 3.5 GHz low noise amplifier.

3.1~10.6 GHz folded-cascode mixer uses a parallel circuit of LC and RLC circuits to achieve wide bandwidth of UWB system and flat conversion gain performance. S11 at 3 to 10 GHz is lower than -10 dB, conversion gain is 1.7 to 6.6 dB, P1dB is -16 dBm, IIP3 is -2 dBm, and power consumption is 10.6 mW.

3.5 GHz folded-cascode mixer inherits the architecture of 3.1~10.6 GHz folded-cascode mixer. It uses a designed active balun to convert single-end input signal into differential signals. This circuit is designed aim at 3.5 GHz for WiMAX. Conversion gain is 6.2 dB, P1dB is -14 dBm, IIP3 is -7 dBm, and power consumption is 16.8 mW.

3.5 GHz low noise amplifier uses forward body bias technique to enhance the performance of this chip with low supply voltage. This circuit is designed aim at 3.5 GHz for WiMAX, too. Gain is 17.6 dB, P1dB is -15 dBm, IIP3 is -6 dBm, noise figure is 2.5 dB, and power consumption is 8.6 mW.

The circuits are implemented by TSMC 0.18μm CMOS process. These chips have also been fabricated by the support of CIC in Taiwan.

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