新興的可變電阻式記憶體已顯示出記憶體內處理能力的巨大潛力，因此在加速 諸如神經網路和神經型態運算之類的記憶體密集型應用方面吸引了相當多的研究興趣。但是，由於可變電阻式記憶體之單元電阻固有的變化差異，基於可變電阻式記憶體的神經網路計算的準確性可能會大大降低。

　　在這篇論文中，我們提出一個協同的演算法架構容錯框架，以全面性解決單元電阻變化差異的問題。具體來說，我們考慮基於可變電阻式記憶體運算的三種主要錯誤類型：非線性電阻分布、靜態變化及動態變化。從演算法層面來看，我們提出一種電阻感知的量化方法，以強制神經網路參數遵循可變電阻式記憶體的精確非線性電阻分布，並引入一種輸入調節技術來補償可變電阻式記憶體的電阻變化。我們還提出了一種選擇性的權重更新方案，以解決運行時發生的動態變化問題。從架構層面來看，我們相應地提出一種通用且低成本的架構，以支持我們的容錯技術。實驗結果顯示，我們提出的三種容錯演算法幾乎沒有準確度損失，並且所提出的架構 產生的性能負擔僅為7.14%。

Emerging Resistive Random Access Memory (RRAM) has shown great potential for in-memory processing power, so they have attracted considerable research interests in accelerating memory-intensive applications such as neural networks and neuromorphic computing. However, due to the inherent variation of the resistance of RRAM cells, the accuracy of neural network calculations based on RRAM may be greatly reduced.

In this thesis, we propose SIGHT, a SynergIstic alGorithm-arcHitecture fault-Tolerant framework, to holistically address the problem of the resistance variation of RRAM cells. Specifically, we consider three main types of faults based on RRAM computing: non-linear resistance distribution, static variation, and dynamic variation. From the algorithm level, we propose a resistance-aware quantization to adjust the neural network parameters to follow the precise non-linear resistance distribution of RRAM, and introduce an input regulation technique to compensate the resistance variations of RRAM. We also propose a selective weight refreshing scheme to address the dynamic variation issue that occurs at run-time. From the architecture level, we accordingly propose a general and low-cost architecture to support our fault-tolerant scheme. Experimental results show that the three fault-tolerant algorithms we proposed have almost no accuracy loss, and the performance overhead of our proposed SIGHT architecture is only 7.14%.

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