在本論文中， 我們將使用不同佈局參數的高壓金氧半場效電晶體(HV-MOSFETs)，討論其不同接面結構對於元件的特性與熱載子可靠度所造成的影響。重要的佈局參數W、L、Lgd與Ovl分別為閘極寬度、閘極長度、飄移區的長度與閘極至薄氧化層之間的長度。
首先，會先闡明本篇論文的研究動機，並簡單介紹高壓元件在業界的應用與優勢。由於元件經常操作在高壓的環境下，對於熱載子可靠度與崩潰機制已成為重要的議題，因此將闡明熱載子效應與元件崩潰的基本原理。為了能夠更深入了解元件內部的物理機制，將使用電腦輔助設計(TCAD)軟體來進行模擬分析與討論。
第二部分將介紹本篇論文研究的元件結構、元件內部區域的定義與量測偏壓的設定，之後透過基本電性的量測，包含線性電流IDlin-Vg、飽和電流IDsat-Vg、截止態崩潰電壓VBD與基板電流Isub-VG，並觀察不同佈局參數對於元件特性的影響。
第三部分將討論不同加速測試與佈局參數對元件退化的影響，我們使用三種固定的汲極電壓VD與閘極電壓VG對應最大Isub值時進行熱載子加速測試，實驗結果也顯示不同接面結構的元件在退化程度上相似，隨著給定VD增加而使退化增大。隨著加速測試的進行，會使得介面缺陷增加，進而使元件內部電位產生變化，讓電場重新分佈，導致離子碰撞率的下降、電流密度下降等等，並產生退化飽和的現象。除此之外，介面缺陷的增加同時也會使得克爾克效應(Kirk effect)的增強。
第四部分將討論不同接面結構的元件的截止態崩潰電壓與熱載子生命週期的變化。實驗結果顯示漸進接面比傳統接面具有更好的截止態崩潰電壓(VBD)，隨著Ovl增加而增大，在經過熱載子加速測試後VBD也有明顯的增加，而熱載子生命週期則是在不同接面結構下具有相似的結果。

In this study, we will use high voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFETs) with different layout parameters to discuss the effects of different junction structures on the characteristics and hot carrier reliability of the devices. The important layout parameters W, L, Lgd, and Ovl represent the gate width, gate length, length of the drift region, and the distance between the gate and the thin oxide layer, respectively.
First, the motivation for this paper will be clarified, and the applications and advantages of high-voltage devices in the industry will be briefly introduced. As devices often operate in high-voltage environments, hot carrier reliability and breakdown mechanisms have become important issue, so the basic principles of hot carrier effects and device breakdown will be explained. In order to gain a deeper understanding of physical mechanisms inside the device, technology computer-aided design (TCAD) will be used for simulation analysis and discussion.
The second part will introduce the device structure studied in this paper, the definition of internal region of the device, and the setting of bias voltages for measurements. Then, basic electrical measurements, including the linear current (IDlin-VG), saturation current (IDsat-VG), off-state breakdown voltage (VBD), and substrate current (Isub-VG), will be performed to observe the effects of different layout parameters on the device characteristics.
The third section will discuss the effects of different acceleration tests and layout parameters on device degradation. We conducted hot carrier acceleration tests using three fixed VD and corresponding VG that resulted in maximum Isub values. The experimental results showed that devices with different interface structures exhibited similar degrees of degradation, which increased as VD increased. As the acceleration test progresses, interface defects increase, causing changes in the internal potential of the device, redistributing the electric field, decreasing the impact ionization rate, and reducing the current density. These changes lead to saturation of degradation. In addition, the increase in interface defects also increases the Kirk effect.
The fourth section will discuss the variation in breakdown voltage (VBD) in the off-state and the lifetime of hot carriers for devices with different interface structures. The experimental results demonstrate that progressive interfaces exhibit better breakdown voltage than traditional interfaces, with an increase in VBD as Ovl increases. After undergoing hot carrier acceleration testing, there is a noticeable increase in VBD. However, the hot carrier lifetime shows similar results for different interface structures.

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