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研究生: 楊楚昀
Yang, Chu-Yun
論文名稱: K-band CMOS低雜訊、功率放大器及60-GHz毫米波可調變增益放大器之研製
Design of K-band CMOS Low-Noise, Power Amplifier and 60-GHz Millimeter-Wave Variable Gain Amplifier
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 58
中文關鍵詞: 低雜訊放大器功率放大器可調變增益放大器
外文關鍵詞: LNA, PA, VGA
相關次數: 點閱:127下載:11
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  • 本論文研究K-band之CMOS低雜訊放大器及功率放大器,以及ㄧ60-GHz之CMOS可調變增益放大器,其中主要是針對汽車防撞雷達系統及60-GHz WPAN 相位陣列天線接收機系統來做設計。15 - 22 GHz CMOS寬頻低雜訊放大器,為一級疊接架構加共源級架構加上一小電感來達到寬頻的效果,而量測結果也做了討論,並猜測問題在於晶片內部地的問題,並針對此問題做討論。研製之兩個K-band CMOS功率放大器,一為24-GHz高效率功率放大器,另一為18-25 GHz CMOS 寬頻功率放大器;K-band CMOS功率放大器為一兩級之疊接架構並針對高功率做設計,量測結果有些許不穩定及頻漂,考慮也是晶片內部地的問題,因此在結果討論中也模擬了此問題;18-25 GHz CMOS 寬頻功率放大器是使用匹配來達到所要之頻寬,量測結果輸入返回損失符合模擬結果,而小訊號增益則與模擬有段差距,此問題在論文中也做了討論。最後為60-GHz CMOS 可調變增益放大器,為了改善其相位對增益之平坦度,使用改良式疊接架構來設計,量測結果上有些許的頻漂及輸出不穩定的問題,雖然如此,但在相位平坦的特性上有表現出來。

    This thesis presents the design of 24- and 60-GHz CMOS amplifier RFICs for millimeter-wave communication applications. The designed RFICs are fabricated with TSMC CMOS 0.18 μm and 90-nm standard processes, respectively. At first for the Ka-band amplifier design, a 15 - 22 GHz wideband CMOS low noise amplifier (LNA), 24-GHz high-efficiency power amplifier (PA), and 18-25 GHz wideband CMOS power amplifier are presented. The simulation and measurement results are compared and discussed. Secondly, a 60-GHz 90-nm CMOS variable gain amplifier (VGA) is presented. For the desired low phase-variation in the variable gain control range, the measured phase-variation of the VGA is less than about 10 degree.

    第一章 緒論 1 1.1 短距離汽車防撞雷達射頻前端簡介 1 1.1.1 短距離汽車防撞雷達研究背景及動機 1 1.1.2 短距離汽車防撞雷達頻帶介紹與實驗室規劃 4 1.2 60-GHz WPAN 相位陣列天線接收機系統簡介 5 1.2.1 60-GHz WPAN 研究背景及動機 5 1.2.3 相位陣列接收機之系統規劃 7 1.3 論文架構 8 第二章 15 – 22 GHz CMOS寬頻低雜訊放大器 9 2.1 低雜訊放大器簡介 9 2.2 寬頻低雜訊放大器簡介 12 2.3 15-22 GHz CMOS寬頻低雜訊放大器 14 2.4 模擬與量測結果 19 2.5 問題與討論 21 第三章 24-GHz CMOS 高效率功率放大器及寬頻功率放大器 23 3.1 功率放大器簡介 23 3.2 一般常見功率放大器架構 24 3.3 24-GHz CMOS高效率功率放大器 27 3.3.1 24-GHz高效率功率放大器設計與製作 28 3.3.2 完整功率放大器設計流程 32 3.3.4 功率放大器結果與討論 36 3.4 18-25 GHz CMOS 寬頻功率放大器 38 3.4.1 寬頻功率放大器完整設計流程 38 3.4.2 寬頻功率放大器模擬與量測結果 42 3.4.3 寬頻功率放大器結果與討論 44 第四章 60-GHz CMOS 可調變增益放大器 45 4.1 可調變增益放大器簡介 45 4.2 一般常見可調變增益放大器架構 45 4.3 60-GHz CMOS可調變增益放大器設計與製作 47 4.4 60-GHz CMOS 可調變增益放大器設計流程 49 4.5 模擬結果 51 4.6 60-GHz VGA量測結果與討論 53 第五章 結論 55 參考文獻 57

    [1] M. Schulze, “Workshop Vehicle Safety Communication,”May, 5, 2005
    [2] http://www.car-safety.org.tw
    [3] “Revision of Part 15 of the Commission’s Rules Regarding Ultra-Wideband Transmission Systems,” FCC,Washington, DC, ET Docket 98-153, Feb 14. 2002.
    [4] A. Babakhani, X. Guan, A. Komijani, A. Natarajan, and A Hajimiri, “A 77GHz 4-element phased array receiver with on-chip dipole antennas in silicon,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb., 2006, pp. 629-638.
    [5] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, Y. Wang, and A. Hajimiri, “A 77GHz phased-array transmitter with local LO-path phase-shifting in silicon,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb., 2006, pp. 639-649.
    [6] J. Lee, Y. Chen, and Y. Huang, “A low-power low-cost fully-integrated 60-GHz transceiver system with OOK modulation and on-board antenna assembly,” IEEE J. Solid-State Circuit, vol. 45, no. 2, pp.264-275, Feb. 2010.
    [7] L. Yang, “60GHz: opportunity for gigabit WPAN and WLAN convergence,” ACM SIGCOMM Computer Communication Review, vol. 39, no. 1, Jan. 2009.
    [8] P. Heydari, “Design and analysis of a performance-optimied cmos uwb distributed lna,” IEEE J. Solid-State Circuit, vol. 42, no. 9, pp.1892-1905, Sep. 2007.
    [9] Q. Liu, J. Sun, Y. J. Suh, s. Kurachi, N. Itoh, and T. Yoshimasu, “A novel current reuse wideband amplifier using 130 nm si cmos technology for 22-29 GHz Application,” in IEEE ICCCAS, July 2009, pp. 807-809.
    [10] K. Yamauchi, K. Mori, M. Nakayama, Y. Itoh, Y. Mitsui, and O. Ishida, “A novel series diode linearizer for mobile radio power amplifiers,” in IEEE MTT-S Microwave Symp. Dig., vol.2, July 1996, pp. 831-834.
    [11] B. Afshar, M. Bohsali, B. Heydari, E. Adabi, A. Arbabian, C. Marcu, and A.-M. Niknejad, 60 GHz CMOS 90 nm Front End & mm-Wave Update, Wireless Research Center, Berkeley.
    [12] G. Hau, T. B. Nishimura, and N. Iwata, “A highly efficient linearized wide-band CDMA handset power amplifier based on predistortion under various bias conditions,” IEEE Trans. on Microwave Theory Tech., vol. 49, pp.1194-1201, June 2001.
    [13] K. Yamauchi, K. Mori, M. Nakayama, Y. Mitsui, and T. Takagi, “Microwave miniaturized linearizer using a parallel diode,” in IEEE MTT-S Microwave Symp. Dig., vol.3, June 1997, pp. 1199-1202.
    [14] S. Ko, and J. Lin, “A linearized casacode CMOS power amplifier,” in IEEE WAMI Conf., Dec. 2006, pp. 1-4.
    [15] C. Lu, A. H. Pham, M. Shaw, and C. Saint, “Linearization of CMOS broadband power amplifiers through combined muligated trasistors and capacitance compensation,” IEEE Trans. on Microwave Theory Tech., vol. 55, no.11, pp.2320-2328, Nov. 2007.
    [16] T. W. Kim, B. Kim, and K. Lee, “Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp.223-229, Jan. 2004.
    [17] T. Sowlati, and D. M. W. Leenaerts, ”A 2.4 GHz 0.18-μm CMOS self-biased cascode power amplifier,” IEEE J. of Solid-State Circuits, vol. 38, no. 8, pp.1318-1324, July 2003.
    [18] C.-Y. Wu, S. W. Hsu, and W.-C. Wang, “A 24-GHz CMOS current-mode power amplifier with high PAE and output power,” in IEEE Circuit and System Symp., May 2007, pp. 2866-2869.
    [19] A. Komijani and A. Hajimiri, “A 24 GHz, +14.5 dBm fullyintegrated power amplifier in 0.18 μm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 561–564.
    [20] J. L. Kuo, Z. M. Tsai, and H. Wang, “A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18 μm CMOS technology”, in IEEE European Microwave Conf., Oct. 2008, pp 1425-1428.
    [21] Y.-N. Jen, J. H. Tsai, C. T. Peng, and T.-W. Huang, “A 20 to 24 GHz +16.8 dBm fully integrated power amplifier using 0.18 μm CMOS process”, IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 42-44, Jan. 2009.
    [22] B. Heydari, M. Bohsali, E. Adabi, and A. M. Niknejad, “A 60 GHz power amplifier in 90nm CMOS technology,” in Proc. IEEE Custom Integrated Circuits Conf., Sept. 2007, pp 769-772.
    [23] B.-W. Min, and G. M. Rebeiz, “A 10-50 GHz CMOS distributed step attenuator with low loss and low phase imbalance,” IEEE J. of Solid-State Circuits, vol. 42, no. 11, pp.2547-2554, Nov. 2007.
    [24] C.-H. Wu, C.-S. Liu and S.-I. Liu, “A 2-GHz CMOS variable-gain amplifier with 50-dB linear-in-magnitude controlled gain range for 10GBase-LX4 ethernet,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, ,Feb. 2004, pp.484 -541.
    [25] K. L. Feng, “Dual-band high-linearity variable-gain ow-noise amplifiers for wireless applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999 pp. 224 -225.

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