以目前64MB DDR SDRAM的工作時脈速度逐漸升高，操作頻率亦已到達200MHz的情況下，其測試所需之時間與成本將大幅提高，因此製作晶圓測試探針卡的公司，皆朝著高速高頻的方向設計，並研發可同時平行測試晶粒的數目越來越多的探針卡，來降低測試所需的成本，但也因此使得訊號的雜訊干擾更加嚴重，像是由於傳輸線不匹配所造成的反射、鄰近兩條傳輸線所產生的串音干擾，還有對於電源端和接地端所造成的瞬間交換雜訊等高頻寄生效應。

　　在本論文中，主要是針對可同時平行測試32顆DDR SDRMA探針卡之電性接觸基板與探針頭作設計，在陶瓷基板上以電磁模擬軟體IE3D及Ansoft HFSS設計所需之傳輸線與穿孔的規格，並利用Maxwell Q3D模擬軟體作訊號完整性分析，以探討探針卡之電性接觸基板與探針頭在傳遞高頻數位訊號時，不會因為高頻寄生效應而造成邏輯訊號的誤判，並符合目前測試廠商的測試標準，最後以自行研發的方式來降低測試所需的成本。

　　Recently, the clock rate of 64MB DDR SDRAM has been reached to 200MHz. In this condition, the cost and time of testing might be increased. In order to overcome these problems, many Probe Card manufacturing companies follow the high-speed and high-frequency issues to design the better products, and increasing the number of high-parallel probe card. But many interferences such as reflection, cross-talk, and simultaneous switching noise (SSN), influence the Probe Card testing.
　
　　The design of Interposer and Probe head on Probe Card, testing 32 die DDR SDRAM simultaneously are proposed in this dissertation. Design the specifications of transmission line and via by IE3D and Ansoft HFSS; then, by using Maxwell Q3D to do Signal Integrity, we can sure that the signal is correct on Interposer and Probe head. Finally, the testing of the “DDR SDRAM” can be cost down by our self-aligned technology.

[1] 何宗憲，”IC測試製程與設備簡介”，機械工業雜誌，189卷，pp.189-203，1998。

[2] S. N, ”A new probe card technology using compliant Microsprings”, Test Conference, Proceedings, International, pp.527-532, 1997.

[3] H. W. Johnson and M. Graham, “High-Speed Digital Design”, A Handbook of Black Magic, PTR Prentice Hall, Inc., 1993.

[4] 謝金明，”高速數位電路設計暨雜訊防制技術”，HP惠普科技叢書，1997。

[5] 柯志祥，”電子構裝電氣特性之電磁模擬與量測”，國立成功大學電機工程研究所碩士論文，民國88年6月。

[6] 李信忠，”電子封裝之電氣特性模型的建立與信號完整性分析”，國立成功大學電機工程研究所碩士論文，民國89年6月。

[7] 黃士釗，”錫球陣列載具電路模型之建立”，國立成功大學電機工程研究所碩士論文，民國92年7月。

[8] L. Martens, ”High Frequency Characterization of Electronic Package”, Kluwer Academic, 1998.

[9] G. A. Katopis, “Delta-I noise specification for a high performance computing machine”, Proc. IEEE, vol. 73, pp. 1405-1415, Sept. 1985.

[10] N. HIRANO, M. MIURA, Y. HIRUTA and T. SUDO, “Characterization and Reduction of Simultaneous Switching Noise for a Multilayer Package”, IEEE Electronic Components and Technology Conference, pp. 949-956, 1994.

[11] Z. Jin, M. K. Iyer, Y. Qin, B. Ooi, and M. Leong, “S-Parameter Based Technique for Simultaneous Switching Noise Analysis in Electronic Package, IEEE Transactions on Advanced Package, vol. 22, pp. 267-273, No.3, August 1999.

[12] D. Cheng, ”Field and Wave Electromagnetic”, Addison Wesley Longman, 1980。

[13] S. H. Hall, G. t W. Hall, and J. A. Mccall, “High-Speed Digital System Design-A Handbook of Interconnect Theory and Design Practices”, John Wiley & Sons, 2000.

[14] G. Gonzalez, “Microwave Transistor Amplifiers Analysis and Design”, Prentice-Hall, Inc. 1997.

[15] ”No boundaries-bring together signal integrity and high frequency design engineers”, Ansoft 2000 HF/SI Workshop.

[16] Maxwell Quick 3D Parameter Extractor User’s Manual, Ansoft Crop. 1994.

[17] 林哲弘，”高速記憶體晶圓測試之線路設計”，國立成功大學
電機工程研究所碩士論文，民國92年6月。

[18] 吳信寬，”高速探針線路之設計”，國立成功大學電機工程研究所碩士論文，民國92年6月。

[19] T. Neu, “Designing controlled impedance vias”, Texas Instruments, 2003.

[20] L. Green, Signal Integrity, IEEE, pp. 195-199, 1998.

[21] J. Lau, C. P. Wong, J. L. Pronce, and W. Nakayama. “Electronic Packaging Design, Materials, Process, and Reliability”, New York: McGraw Hill, 1998.

[22] S. C. Hinkle, J. A. “Package lead inductance considerations in high speed applications”, 1987.

[23] J. C. Steve M. “Capacitor selection and EMI filtering”, AVX Corporation, Myrtle Beach, SC, 1997.

[24] C. J. H., Reader, H. C., “Transients on multiconductor transmission lines above dissipative earth-numerical simulation and measurement”, Electromagnetic Compatibility, IEEE Transactions on, Volume, 45, Issue, 2,
May 2003.

[25] S., D. P., et, Al, “Principles of electronic packaging”, Mc Grew Hill Co, 1989.

[26] S. H. Russ and C. O. Alford, “Coupled noise and its effects on modern packaging technology”, IEEE trans on components, hybrids, and manufacturing technology, Vol. 13, No. 4, December 1990.