掃瞄式電子顯微鏡已逐漸廣泛地被應用在先進的超大型積體電路製造中之製程缺陷偵測。尤其是當元件尺寸越做越小，底層之傳導連線越容易在製程中斷線，半斷線，短路，或漏電而於日後造成失效或可靠性不良之元件。此類缺陷大多無法於該製程完成後由晶圓表面測得，傳統的光學晶圓表面的缺陷檢測技術已受到限制。掃瞄式電子顯微鏡缺陷檢測技術是目前唯一被應用於量產的生產線上作為製程後底層電性缺陷的偵測工具。其對積體電路的足夠靈敏度已使其漸成為先進晶圓廠中確認其製程成效的不可或缺的角色。
電子顯微鏡缺陷檢測技術可應用其材料對比及高解析度成像而檢測出當站製程之表面物理性缺陷，此能力與傳統的光學缺陷檢測互有長短，而通常是較優。而其不可被取代之主要特性為利用其有電壓對比成像之特性而能偵測得無法於晶圓表面上看到的積體電路內之異常的連結通路。
本論文分別探討先進電子顯微偵測技術於互補式金屬氧化物半導體製程中的普遍應用。在前段製程常出現的底層接觸窗斷線及部分斷線進行成功檢測，並針對成像的灰階相對於斷線程度進行比較，並進而得其線性關係。對於90奈米或65奈米線徑以下之前段製程常見之矽化鎳成管狀鑽出之縱向分佈作了深入的實驗探討。在65奈米線徑以下前段製程常見之多晶矽閘極與其旁之接觸窗短路之偵測技術作一系列條件測試終能順利測得。
在後段製程常出現的底層通道斷線及部分斷線進行成功檢測。部分晶圓廠為了防止金屬氧化而在金屬研磨後再過了下一站沉積上一層氮化矽或滲碳氮化矽後才作電子顯微鏡檢測之偵測技術也作了實驗探討，並針對成像的灰階相對於斷線程度進行比較，並進而得其線性關係。。
電子顯微鏡缺陷檢測技術在應用上也有其限制。實驗量化其受到電磁波干擾的現象。另也做了實驗證明在電子顯微鏡掃瞄後的晶片其下一站不應安排進行水洗。對於某些條件可能會造成晶片被電弧破壞或造成污染也進行實驗探討。

SEM (Scanning Electron Microscope) has been getting widely applied to process defects detection on advanced ULSI manufacturing. Especially when the device scale is getting smaller, the easily underneath wiring disconnecting, half-disconnecting, short, or leak would happen during processes and leads to device failure or poor reliability. Most of the defects mentioned above cannot be detected on the wafer surface after the process steps. The traditional optical wafer surface defect detection technologies are limited on these applications. Currently SEM defect detection technology is the only tool applied on mass production line to detect the underneath electrical defects after the process steps. Its good sensitivity to the integrated circuit has made itself to be a necessary role to confirm the process results in an advanced manufacturing fab.
The material contrast and the high resolution image of e-Beam can be applied to catch the surface physical defects on the current process step. This capability is similar or better than the traditional optical defect detection. The main characteristic of e-Beam defect detection technology that can not be substituted is the VC (voltage contrast). It can be used to detect the abnormal electrical connection that can not be seen on the wafer surface.
The general applications of e-Beam defect detection technology on the CMOS processes have been individually discussed. Contact open and contact partial open which usually happen in front-end processes were successfully caught. Further comparison between the gray-level magnitudes of the e-Beam defect images and the contact open statuses has shown the linear relation between them. NiSi piping is a type of front-end process defects often seen beyond 90nm or 65nm devices. The vertical distribution of NiSi piping has been studied with experiments. The short between the poly gate and the contacts beside is another common seen defect happens beyond 65nm devices. There were a series of e-Beam condition tests and could eventually be detected.
Via open and via partial open which were back-end processes were successfully caught. Further e-Beam defect detection technology on the post metal CMP cap with SiCN has been studied. Some fabs do e-Beam inspections on SiCN cap post metal CMP instead of on metal layer to prevent metal oxidation. Further comparisons between the gray-level magnitudes of the e-Beam defect images and the via open statuses has shown the linear relation between them.
There are some limitations of e-Beam defect defection applications being studied. The experiment showed the e-Beam performance was interfered with the magnetic field. It has been also proven that DI water clean after e-Beam inspection would generate Carbon-rich defects on the wafer. Some special column condition settings would have more chances to cause the arcing happening in the chamber and damage or contaminate the wafer.

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