| 研究生: |
洪國欽 Hung, Kuo-Chin |
|---|---|
| 論文名稱: |
降低產品因 HDP defect 造成的報廢率 Reduce product scrap rate due to HDPCVD issue |
| 指導教授: |
張守進
Chang, Shoou-Jinn |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系碩士在職專班 Department of Electrical Engineering (on the job class) |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 中文 |
| 論文頁數: | 55 |
| 中文關鍵詞: | 淺溝渠隔離 、缺陷 |
| 外文關鍵詞: | STI, defect |
| 相關次數: | 點閱:107 下載:50 |
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本論文主要研究半導體奈米製程中,在淺溝渠隔離 (Shall Trench Isolation, STI) 薄膜沉積過程中所產生的微塵缺陷之改善。在此沉積過程中所產生的微塵缺陷由於無法即時被有效偵測而無法執行任何彌補措施,因此一但發現微塵缺陷情況過於嚴重,就只能將產品報廢。這種情況對半導體奈米製程良率及工廠生產過程造成不良後果,不但會大幅增加生產成本,且會延遲產品交貨時間,嚴重影響客戶在新世代產品推出的競爭力,同時會毀壞自己的商譽及客戶的信任。
淺溝渠隔離在半導體奈米製程中是至關重要的技術,主要目的是沉積氧化層用來隔離P-WELL 以及N-WELL。隨著半導體線寬越來越窄,淺溝渠隔離的深寬比也越來越大,因此薄膜沉積設備的填洞能力也變得越來越重要。一般傳統的 PECVD (Plasma Enhanced Chemical Vapor Deposition) 無法滿足高深寬比的填洞能力 (gap fill) 需求,因此必須使用HDPCVD (High Density Plasma Chemical Vapor Deposition) 搭配不同的沉積模式及過程來達成目的。
本論文探討及研究半導體製程,使用HDPCVD沉積氧化層淺溝渠隔離薄膜的過程中,微塵造成缺陷的機制及其改善方法。
In this thesis, the semiconductor nanometer process, the shallow trench isolation, (STI) improvement of the fine dust produced defects in the thin film deposition process. The fine dust produced in this deposition process defects not readily be effectively detected and can’t perform any remedies, but found dust defects too serious, it can only be scrapped. This case adverse consequences on the of semiconductor nanometer process yield and factory production process, not only a substantial increase in production costs, and will delay the delivery time, seriously affect the competitiveness of customers in the launch of a new generation of products will also destroy themselves goodwill and trust of customers.
Shallow trench isolation is critical in the semiconductor nanometer process technology, the traditional PECVD (Plasma Enhanced Chemical Vapor Deposition) unable to meet the capacity needs of high aspect ratio to fill the holes, so you must use HDPCVD (High Density Plasma Chemical Vapor Deposition) to achieve this objective.
This thesis is to explore and examine the semiconductor manufacturing process, the shallow trench isolation process of thin film deposition, about dust caused by defective mechanism and its improvement.
參考文獻
[1] Li LS, Walda J, Manna L, Alivisatos AP. “Semiconductor nanorod liquid crystals” Nano Letters ,vol 6, 2002 , pp.557-560.
[2] Peng KQ, Zhu J , “Simultaneous gold deposition and formation of silicon nanowire arrays” Journal of Electroanalytical Chemistry ,vol 558, 2003 , pp.35-39.
[3] 莊達人,”VLSI製造技術”,高立圖書股份有限公司,1995年。
[4] Wenting Liu , Zhengtang Liu, Feng Yan, Tingting Tan, Hao Tian,” Influence of O2/Ar flow ratio on the structure and optical properties of sputtered hafnium dioxide thin films”, Surface & Coatings Technology 205 (2010).
[5] Nathaniel J. Quitoriano, Miro Belov, Stephane Evoy, and Theodore I. Kamins,” Single-Crystal, Si Nanotubes, and Their Mechanical Resonant Properties”, Nano Letter, 2009.
[6] M. Zubertn, L. Starzak, G. Jablonski, M. Napieralska, M. Janicki, T. Pozniak, A. Napieralski,” An accurate electro-thermal model for merged SiC PiN Schottky diodes”, Microelectronics Journal 43 (2012) p.312–320.
[7] J. Robertson,” High dielectric constant oxides”, Eur. Phys. J. Appl. Phys. 28, 265–291 (2004).
[8] 洪昭南、郭有斌,”以化學氣相沉積法成長半導體薄膜”,化工技術,2000年。
[9] Hong Xiao 著,羅正忠、張鼎張譯,”半導體製程技術導論”,歐亞書局,2002年。
[10] 洪昭南、郭有斌,”電漿反應器與原理”,化工技術,2001年。
[11] 林明獻,”矽晶圓半導體材料技術”,台灣,全華科技圖書股份有限公司,2007年。
[12] J.D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology-Fundamentals, Practice and Modeling, Prentice Hall, New Jersey, 2000.
[13] Novellus System, Dielectric CVD process (training manual), 1997
[14] John L. Vossen and Werner Kern, Thin Film Process, Part II, Academic Press, 1978.
[15] S. Sivaram, Chemical Vapor Deposition Thermal and Plasma Deposition of Electronic Materials, Van Nostrar Reinhold, International Thomson Publishing Inc., New York, 1995.
[16] S. Wolf, Silicon Processing for the VLSI Era Volume II-process Integration, Lattice Press, CA, 1990.
[17] C.Y. Chang and X.M. Sze, VLSI Technologies, McGraw-Hill, New York, 1996.
[18] S.M. Sze, VLSI Technology, 2d ed., McGraw-Hill Companies, Inc., New York, 1988.
[19] S. Wolf and R.N. Tauber. Silicon Processing for the VLSI Era Volume I-Process Technology, Lattice Press, CA, 1986.
[20] M. Quirk and J. Serda, Semiconductor Manufacturing Technology, Prentice Hall, New Jersey, 2001.
[21] H. Xiao, Introduction to Semiconductor Manufacturing Technology, Prentice Hall, New Jersey, 2001.
[22] K. H. A. Bogart, J. P. Cushing and Ellen R. Fisher, Chemical Physics Letters, Volume 267, 1997, Pages 337, 383.
[23] 張忠樸,實驗計畫速學活用法,台北,電路板資訊雜誌,2000年。
[24] 吳復強,田口品質工程,台北,全威圖書有限公司,2002年。
[25] 李輝煌,田口方法-品質設計原理與實務,台北,高立圖書有限公司,2000年。
[26] 鄭燕琴,田口品質工程技術理論與實務,中華民國品質管制學會,1993年。
[27] Douglas C. Montgomery, “Design and analysis of experiments”, John Wiley, 2001.
[28] Francis F. Chen, Introduction to Plasma Physics and Controlled Fusion, Vol. 1, 1984.
[29] Michael A. Lieberman and Allan J. Lichtenberg, Principles of Plasma Discharges and Materials Processing, 2 Edition, Wiley Interscience, Hoboken, NJ. Wiley, 2005.
[30] Jansen, F.,”AVS short Course PECVD”, American Vacuum Society, 1990.
[31] Brain Chapman, Glow Discharge Processes, John Wiley and Sons, 1980.
[32] J Reece Roth, Industrial Plasma Engineering Volume 2, 2991. P335
[33] A Szeleres and S Alexandrova, Vacuum, Vol. 47, Issue 12, 1996, p.1483-1486.
[34] J. P. Joly, “Metallic Contamination of Silicon Wafers”, Microelectronic. Eng., 1998.
[35] J. H. Keller, Vacuum Science and Technology, 1993.