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研究生：	林建廷 Lin, Chien-Ting
論文名稱：	先進應變工程及完全金屬矽化閘極應用於奈米金氧半電晶體的之研究 The Study of Advanced Strain Engineering andFUSI-gate for Nano Meter CMOSFET Technology Applications
指導教授：	葉文冠 Yeh, Wen-Kuan 方炎坤 Fang, Yean-Kuen
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	78
中文關鍵詞：	金氧半電晶體、金屬矽化閘極
外文關鍵詞：	CMOSFET, 90nm, FUSI-gate
相關次數：	點閱：158 下載：2
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當金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistor)的尺寸進入奈米等級時，為增進元件性能,提昇載子的移動率，應變工程 (Strain engineering)已漸成為量產的必要技術。本論文中對應變工程做更完整的探討，並首度提出數種新的先進應變工程方法。除外，金屬閘極 (metal gate) 亦是奈米等級電晶體量產必要技術之一，在此我們也提出一簡單製作金屬矽化閘極之技術，此技術非常符合奈米等級IC製程。本研究並將吾人研發的先進應變工程 (Strain engineering)及完全金屬矽化(Fully Silicided, FUSI) 閘極運用於提昇奈米金氧半導體元件之特性以驗証其實用性。
首先探討應力技術對元件的效能之影響，包括金屬矽化閘極之相位變換(phase transfer)感應應力，二次應力技術(second CESL)感應應力，以及CESL 移除所遺留之感應應力。接著，我們提出一簡單之金屬矽化閘極上製程技術配合矽能帶邊緣功函式 (band-edge work functions)同時完成N/PMOSFET 元件之設計。然後在實驗中，探討CESL 應力對部分空乏型矽絕緣層金氧半電晶體元件PD-SOI (partially depleted silicon-on-insulator)特性的影響，經由電性與模擬分析，探討不同矽厚度TSI (SOI silicon thickness) 對元件特性的影響。除外這些結果對完全空乏型矽絕緣層金氧半電晶體元件FD-SOI (fully depleted SOI) 與多閘極multi-gate MOFET 之設計也有幫助。另外我們並探討淺溝槽絕緣層
(Shallow trench Isolation (STI)) 應力對元件遷移率(Mobility)之影響，結果發現STI 與 CESL stress 在不同擴散長度 LOD (length of diffusion)下對N/PMOSFET 的遷移率有不同之影響。最後，我們製作結合CESL應變技術與凹陷式閘極(Notched-Gate)技術的金氧半電晶體，分別探討不同閘極結構對於元件特性的影響。實驗証實，應用了CESL 應變技術及Notched-Gate 結構的元件其特性皆優於傳統閘極元件。

In this dissertation, we study the impact of strain engineering and FUSI-gate technologies on nano meter scale MOSFETs performances in detail. The study is divided in five parts. First, we propose three types of the new strain engineering in FUSI-gate MOSFET. Three strain sources on FUSI are studied and analyzed, including enveloped FUSI phase transfer induced stress, the second-CESL induced stress, and the first CESL on poly-gate top
removed by FUSI CMP. Second, we propose a simple CMOS FUSI process, which has the work function near to the N or PMOSFET band-edge, and is fully compatible with the conventional CMOSFET technology. Third, we extensively investigate the impact of CESL strain engineering on the PD-SOI (partially depleted silicon-on-insulator) devices with various TSI (SOI silicon thickness). We found the related device characteristics are supported by (IV)
simulation data. Besides, the results are also important for the study of CESL strain engineering on FD-SOI (fully depleted SOI) and multi-gate MOFET design. Fourth, we study the interactions of STI stress with various mobility
enhancement approaches systematically. The interaction between STI (shallow trench isolation) stress and CESL stress is significant, and results in a different LOD (length of diffusion) mobility trend for NMOSFET and
PMOSFET, respectively. Finally, impacts of the notched-gate structure on contact etch stop layer (CESL) stressed 90nm NMOSFET were studied in detail. Based on both of simulation and measurement, a notched-gate structure
with the high tensile-stress CESL enhances the driving capability, SCE, and DIBL of the device but without increasing the leakages obviously.

中文摘要	(I)
Abstract	(III)
目錄(CONTENTS)	(V)
Table Captions	(VII)
Figure Captions	(VIII)
Chapter 1	Introduction	1
	1-1 Background	1
1-1.1 Strain Engineering	                        2
1-1.2 Fully Silicided Gate (FUSI-gate)	2
	1-2 Preface of this Dissertation	3
Chapter 2	Novel FUSI Strained Engineering for Enhancement of the 45-nm Node CMOSFET Performances	6
	2-1 Introduction	6
	2-2 Processes and Device Fabrication	6
2-3 Enveloped FUSI phase transfer induced stress	7
2-4 The second CESL induced stress	9
2-5 The first CESL on poly-gate top removed by FUSI CMP	10 
2-6 Summary	11
Chapter 3	CMOS Dual Work Function Engineering using Implanted Ni-FUSI	25
3-1	Introduction	25
3-2	Process and Device Fabrication	25
3-3	Results and Discussion	26
3-4 Summary	27


Chapter 4	Effect of Silicon Thickness on Contact Etch Stop Layer Induced Silicon/Buried Oxide Interface Stress for Partially Depleted SOI CMOSFET	34
4-1	Introduction	34
4-2	Process and Device Fabrication	35
4-3	Results and Discussion 	35
4-4	Summary	36
Chapter 5	Investigation and Modeling of Stress Interactions on the 90 nm SOI CMOSFET with Various Mobility Enhancing Approaches	42
5-1	Introduction	42
5-2	Experimental	43
5-3	Results and discussion	44
5-4	Summary	47
Chapter 6	Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90nm nMOSFET	58
6-1	Introduction	58
6-2	Experiment	59
6-3	Results and Discussion	59
6-4	Summary	61
Chapter 7	Conclusions and Prospects	66
7-1	Conclusions	66
7-2	Prospects	67
Reference		70
Appendix A	Author’s Resume
Appendix B	Author’s Related Publications
                                    

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