隨著科技的發展，電子產品不斷追求高性能、低成本、薄小化及多樣化，半導體元件尺寸的微縮已不是唯一的方式，導入應變矽技術能有效提升元件效能且成本不高。因此，應變矽技術為現今半導體研究發展的重要方向之一。

應變矽技術藉由應力源對矽通道產生拉伸或壓縮應力的方式來提升元件載子遷移率。本文使用ANSYS 12.0有限元素分析軟體，模擬分析局部應變矽技術中含碳量1.3%的矽碳源/汲極(SiC S/D)應力源及1GPa拉伸應力的接觸蝕刻停止層(CESL)應力源，對NMOS通道產生之應力作用，及探討兩者應力源彼此對通道應力分佈情形的影響。然後，與文獻進行驗證評估。

其次，針對NMOS結構中的S/D深度、S/D長度、S/D高度、S/D碳含量、閘極長度、閘極高度、通道長度、通道寬度、Spacer形狀、CESL厚度等十個因子進行單一因子分析，藉由壓阻係數及各方向應力值來評估各因子對載子遷移率增益的影響。分析結果顯示，增加S/D深度、增加S/D碳含量、減少閘極長度、增加閘極高度、減少通道長度、增加通道寬度，皆能有效提升遷移率。

最後，利用田口品質工程方法，透過直交表實驗及變異數分析找出重要因子與最佳製程參數組合，以達到提升載子遷移率之目的。最佳製程參數組合的載子遷移率增益為27.19%，而原始製程參數設計為20.16%，提升了34.87%，對NMOS元件效能有明顯之改善。

With the development of science and technology, high-performance, low cost, mini-size and multi-functions have become the consistent goals for the electronic products. To reach these goals, Scaling down the size of the semiconductor device shouldn’t be the only way anymore. Instead, strained technology is capable to effectively enhance device performance and lower cost. Therefore, strained technology is recognized as an important direction of semiconductor research and development nowadays.

For the strained technology, the stressor is applied to induce tensile stress or compressive stress in Si channel to enhance the carrier mobility of components. By adopting the ANSYS 12.0 finite element analysis software, this study simulates the stresses induced by the silicon-carbon alloy source/drain(SiC S/D) stressor with the carbon content of 1.3% and 1GPa tensile stress contact etch stop layer (CESL) stressor in NMOS Si channel. Besides, the effects of two stressors on the stress distribution in the channel are investigated. Then, the result is verified and evaluated with literatures.

Secondarily, the single-factor analyses for 10 factors in the NMOS Structure, S/D depth, S/D length, S/D height, S/D carbon content, gate length, gate height, channel length, channel width, spacer shape and CESL thickness are conducted. The effect of each factor on the carrier mobility of components is investigated by the piezoresistive coefficient and stress at each direction. The results show that the mobility can be improved by increasing S/D depth, S/D carbon content, gate height, channel width and reducing the gate length and channel length as well.

Finally, The Taguchi quality engineering method is applied. By orthogonal array experiments and analysis of variance, the important factors and the optimal parameter combination are obtained to achieve the enhancement of carrier mobility. As a result, the optimal parameter design mobility gain in Si channel becomes 27.19%, which shows a 34.87% increase of the original mobility gain of 20.16%. Therefore, the performance of the NMOS device has been significantly improved.

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