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研究生：	柯伯賢 Ke, Po-Hsien
論文名稱：	氮化二氧化鈦作為電荷捕捉層在非揮發性記憶體中之研討 Nitrided TiO2 as Charge Trapping Layer for Nonvolatile Memory Devices
指導教授：	陳貞夙 Chen, Jen-Sue
學位類別：	碩士 Master
系所名稱：	工學院 - 材料科學及工程學系 Department of Materials Science and Engineering
論文出版年：	2014
畢業學年度：	102
語文別：	中文
論文頁數：	125
中文關鍵詞：	電荷捕捉式記憶體、氮化二氧化鈦、捕獲能態
外文關鍵詞：	Charge Trapping Memory, Nitrided Titanium Oxide, Trapping sites
相關次數：	點閱：93 下載：4
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傳統非揮發性記憶體是以複晶矽(poly-silicon)浮閘極為電荷儲存單元的快閃式記憶體為主，在元件尺寸微縮時，快閃式記憶體將產生電荷遺漏的現象。為克服此問題，近來提出之MONOS(Metal-oxide-nitride-oxide-silicon)薄膜非揮發性記憶體，即以氮化高介電常數薄膜作為電荷捕捉層，由於其較穩固的電荷儲存能力，可縮減穿隧氧化層膜厚，以利降低元件操作電壓，提升元件操作速率，並同時兼顧可靠性。
本實驗以磁控濺鍍之方式成功製備電荷捕捉層，TiO2及TiON，用以探討非揮發性電荷捕捉式記憶體之載子捕獲效應與其應用特性。首先於矽基材以乾式熱氧化法成長SiO2穿隧層，接續以濺鍍製備TiO2或經氮化之TiON電荷捕捉層，旋即接續濺鍍上SiO2阻絕層，之後於全氧環境下900℃熱處理一分鐘，最後沉積上鋁金屬閘極電極以完成MONOS元件製程。研究中使用精密阻抗分析儀量測元件電容-電壓與耗散係數(Dissipation factor)-電壓特性曲線；半導體參數分析儀量測元件電流-電壓特性曲線，並以脈衝產生器施予元件暫態操作偏壓以獲取元件電性行為。在材料分析方面，以高解析穿透式電子顯微鏡(HRTEM)觀測疊層元件之橫截面，以瞭解其實際膜厚、氧化層晶相形貌與界面微結構，並搭配X光電子能譜儀(XPS)了解介電薄膜及中介層之組成。
透過HRTEM橫截面圖，得取疊層介電薄膜[SiO2/TiO2(or TiON)/SiO2]厚度分別為3nm/3nm/15nm。各介電層薄膜均為非晶質材料，可免於晶界生成而為漏電途徑。經由Ti2p與O1s XPS能譜分析TiO2電荷捕捉層/ SiO2穿隧層界面，可知有一中介層生成，為Ti、Si和O反應生成之鈦矽酸鹽(Ti-Silicate)。再者，經由Ti2p、O1s與N1s XPS能譜可說明若於濺鍍過程中加入氮氣，確實有效摻入氮原子形成TiON電荷捕捉層。並可見以TiON作為電荷捕捉層時，由於氮化處理可鈍化界面，避免與鄰近SiO2疊層材料產生互擴散反應，而生成鈦矽酸鹽類中介層，並模糊接面清晰度。
在電性表現方面，相較於TiO2，以TiON作為電荷捕捉層時，由其優異的C-V(Capacitance-Voltage)曲線遲滯窗口寬度、暫態電壓寫入/抹除效率與記憶時效能力，顯示氮原子置入TiO2中，可誘發更多且深層載子捕獲能態，因此優化電荷捕捉層載子捕捉能力。再者，由變頻與變溫C-V曲線遲滯窗口大小之變化，指出氮化處理有效置入深層載子捕獲能態。而從變頻與變溫D-V(Dissipation factor-Voltage)曲線峰值變化，可說明氮化有助降低電荷捕捉層與穿隧層界面缺陷能態形成以減少耗散係數，並穩定電荷捕捉層於高溫下記憶特性，有助於實際應用之發展。此外，由變溫下I-V量測，TiON電荷捕捉層漏電程度隨溫度變化並不顯著，證實其擁較佳之薄膜特性並免於與SiO2穿隧層產生鈦矽酸鹽類中介層之生成。
本實驗說明以TiON作為非揮發性記憶體的電荷捕捉層，確實可製備出高效能、擁長時效之電荷捕捉式記憶體，並說明於不同溫度下的載子捕捉特性，以評估此記憶體於積體電路產業中應用之可行性。

Abstract
Flash memories using poly-silicon as charge storage layers are the mainstream of conventional nonvolatile memories (NVM). However, flash memories face the difficulty in continued dimension down-scaling because of sidnificant charge losses through the floating gate. Therefore, MONOS nonvolatile memory devices have been developed to resolve the issue. Owing to their reliable charge storage capability, nitrided charge trapping layers promise to use thinner tunnelling oxide without losing the nonvolatility, and consequently to lower operating voltage and increase operating speed.
In this thesis, we have successfully fabricated MONOS CTM (charge trapping memories) with an Al/ SiO2/ TiO2 (or TiON)/ SiO2 /Si structure. After a standard Radio Corporation of America (RCA) cleaning, a 3-nm SiO2 as a tunneling layer (TL) was grown on the silicon substrate by thermal dry oxidation. Then, a 3-nm TiO2 (or TiON) charge trapping layer (CTL) was deposited on the SiO2 by RF sputtering a pure Ti target in a pure O2 or mixed N2/O2 (2:1) ambient. Following that, 15-nm SiO2 blocking layer was deposited by RF sputtering a pure Si target in a pure O2 ambient. Then, the dielectric stacks went through a post deposition annealing in O2 ambient at 900℃ for 1 min. Finally, Al was sputtered and patterned as a gate electrode.
All electrical measurements were carried out under a light-tight and electrically shield condition. The current density-voltage (J-V) curves were measured with the Agilent 4156 C semiconductor parameter analyzer. The capacitance-voltage (C-V) and dissipation-voltage (D-V) curves were measured with the Agilent 4294A LCR meter. The program/erase operations were done with Agilent 81101A pulse generator. The material characteristics of the high-k dielectric films were analyzed by transmission electron microscopy (TEM) and the X-ray photoelectron spectroscopy (XPS). HRTEM cross-section images of the MONOS capacitors confirm the physical thickness of the charge-trapping film for both TiO2 and TiON CTMs is 3nm. The blocking layer and tunneling layer are 15 and 3nm, respectively. Compare with the TiON one, there is an apparent interlayer at the CTL/TL interface for the TiO2 CTM, which can be futher confirmed by the XPS analysis. XPS spectra illustrate that sputtering with a nitrogen containing ambient does effectively incorporate nitrogen into TiO2 to form TiON. XPS analysis also reveals a Ti-silicate interlayer formed at the CTL/TL interface of the TiO2 CTM, but not in the TiON one. This can be ascribed to the suppression of elemental inter-diffusion owing to the nitrogen incorporation in TiO2.
The excellent electrical performances (large C-V hysteresis memory window, high program/erase speed, and long retention) for TiON CTM indicate that nitrogen incorporated TiON CTL contains more and deeper trapping states in its band-gap, leading to its superior charge trapping capability as compared to the TiO2 CTL. I-V characteristics at variable temperatures (25-100℃) indicates that the leakage current of TiO2 CTM increases substantially with increasing temperature, but the leakage current of TiON CTM only increases slightly with increasing temperature. This observation can be attributed to the Ti-silicate formed at the TiO2-CTL/SiO2-TL interface, which becomes a charge loss path to degrade the leakage current. The silicate-facilitated charge loss also leads to the continuously shrunk C-V hysteresis memory window of TiO2 CTM with increasing temperature, while the memory window of TiON CTM becomes winder with increasing temperature.
This study demonstrates that the TiON CTL fabricated by reactive sputtering in mixed N2/O2 (2:1) ambient will efficiently trap charges and inhibit the CTL/TL interfacial reaction, which is highly potential for high-performance charge-trapping nonvolatile memory application.

Summary
To fulfill the requirements of future Metal-oxide-nitride-oxide-silicon-type nonvolatile memories, e.g., large memory window, fast program/erase efficiency, and good data retention, extensive researches have been followed out to deliver high-k dielectrics for substituting Si3N4 as the charge-trapping layer (CTL) of MONOS memories, such as TiO2, HfO2, NiO, and Ga2O3, mainly due to their high charge-trapping capacity and appropriate conduction-band offset to silicon.

In this work, electrical characteristics of TiO2 and nitrided TiO2 (TiON) as the CTL of MONOS memories are investigated. The interface quality, composition, and crystallinity of stack dielectric film are examined by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS memory device without nitrogen incorporation in CTL, the one with nitrided TiO2 showed a wider memory window, a higher program speed with a low gate bias, and a fewer charge loss mainly due to nitrogen incorporation, which induces deeper charge trapping sites in the nitrided TiO2 film. In addition, the nitrided TiO2 will reduce shallow traps near the CTL/SiO2 interface, owing to the effective suppression in the formation of titanium silicate at the TiO2/SiO2 interface by nitrogen passivation.

總目錄
第一章 緒論1
1-1 研究背景1
1-2 研究目的5
1-3 論文架構6
第二章 文獻回顧7
2-1 高介電常數材料在閘極介電層之應用7
2-2 半導體記憶體13
2-3快閃記憶體16
2-3.1概述16
2-3.2基礎原理17
2-3.3寫入/抹除機制19
2-3.4元件可靠性23
2-3.5元件組織結構24
2-3.6元件尺寸微縮面臨之挑戰25
2-4 電荷捕捉式記憶體37
    2-4.1概述37
    2-4.2氮化效益於電荷捕捉層相關文獻研討 39
2-5 氧化鈦材料基本性質44
第三章 實驗方法與步驟49
3-1 簡介49
3-2 實驗材料51
3-2.1基材(substrates)51
3-2.2濺鍍靶材(target)51
3-2.3濺鍍及熱處理環境氣氛51
3-2.4實驗藥品與耗材52
3-3 實驗設備53
3-3.1乾式熱氧化系統(Dry oxidation system)53
3-3.2濺鍍系統(Sputtering system)54
3-4實驗流程56
3-4.1基材清洗(Substrate cleaning)56
3-4.2介電薄膜製備(Dielectric film fabrication)56
3-4.3 MONOS電容器製備58
3-5 分析儀器59
3-5.1四點探針儀(Four-point probe)59
3-5.2表面粗度儀(Stylus profilometry)60
3-5.3橢圓偏光儀(Eillipsometer)61
3-5.4 X光光電子能譜儀(XPS)62
3-5.5穿透式電子顯微鏡(TEM)64
3-5.6精密阻抗分析儀(Precision impedance analyzer)65
3-5.7半導體參數分析儀(Semiconductor parameter analyzer)67
3-5.8脈衝產生器(Pulse generator)68
第四章 結果與討論69
4-1 研究動機69
4-2 實驗製程與條件70
4-3 材料分析72
4-3.1微結構分析72
4-3.2成分分析76
4-4 電性分析84
4-4.1電荷儲存效益與電容-電壓曲線之關聯性84
4-4.2電容-電壓遲滯曲線中之電荷遷移89
4-4.3寫入/抹除效率98
4-4.4頻率變化於電荷捕捉上之影響102
4-4.5溫度變化於電荷捕捉上之影響106
4-4.6漏電流特性109
4-4.7電荷保存時效特性111
第五章 結論114
參考文獻116



  
表目錄
Table 1-1 International Technology Roadmap for Semiconductor (2011 update)[3]4
Table 2-1 Summary of Semconductor memory[40]15
Table 2-2 Performance comparison between NOR and NAND flash34
Table 2-3 Properties of TiO2 with three kinds of structure[68]45
Table 3-1 Sequence of modified RCA cleaning procedure57
Table 4-1 The nomenclature for samplesof MONOS NVM with TiO2 or TiON CTL71
Table 4-2 Summary of binding energy for XPS79
  
圖目錄
Fig. 1-1 Relationship between gate current density (A/cm2) and gate voltage (V) with different SiO2 gate dielectric thickness[7]4
Fig. 2-1 Moore’s law as expressed by the number of transistors per chips[22]11
Fig. 2-2 Calculated band offset for a number of potential high-k gate dielectric materials to Si[28]11
Fig. 2-3 Plot of dielectric constant versus optical bandgap Eg, optical of alternative gate dielectrics that likely are stable in contact with silicon[29]12
Fig. 2-4 Schematic of important regions of a field effect transistor gate stack[26]12
Fig. 2-5 Categories of Semiconductor memory14
Fig. 2-6 Comparison of NOR and NAND flash memories[source:Toshiba]26
Fig. 2-7 Application of Flash memory for consumer electronics[source:Toshiba]26
Fig. 2-8 Schematic cross section of Flash cell27
Fig. 2-9 Reading operationcurve of Flash memory27
Fig. 2-10 Energy band diagrams of a MONOS transistor under (a) positive and (b) negative gate bias28
Fig. 2-11 (a) Schematic cross-section of nanocrystal memory device structure; (b) illustration of write process:accumulation-layer electron tunnels into the nanocrystal; (c) illustration of erase process:inversion-layer hole tunnels into the nanocrystal, electron in nanocrystal can tunnel back to the channel[46]29
Fig. 2-12 MONOS idea energy band diagram[26,62]29
Fig. 2-13 Four approaches to programming methods, described bu Hu and White[47]30
Fig. 2-14 Energy band diagram of Frenkel-Poole emission[54]31
Fig. 2-15 Schematic cross section of a MOSFET. The energy distribution function at point(X1, Y1) is also shown[43]31
Fig. 2-16 The equivalent circuit and cross-section of NOR array flash[60]32
Fig. 2-17 NOR flash memory operation methods32
Fig. 2-18 The equivalent circuit and cross-section of NAND array flash[60]33
Fig. 2-19 NAND flash memory operation methods33
Fig. 2-20 SEM image of U-shaped floating gate poly-Si structure[59]35
Fig. 2-21 Gate coupling ratio as a function of design rule[59]35
Fig. 2-22 Required floating-gate height for suppression coupling interferences and coupling ratio by design rule[59]36
Fig. 2-23 Reduced floating gate interference due to low-k dielectric material[61]36
Fig. 2-24 Schematic structure of MONOS device38
Fig. 2-25 (a) Vth as a function of retention time at two different temperatures, such as 150 and 250℃ for the OHA devices. (b) Calculated trap density vs trap level of HfON[67]43
Fig. 2-26 Bulk structures of Rutile、Anatase and Brookite[63]46
Fig. 2-27 Assessed Ti-O phase diagram[65]47
Fig. 2-28 Ternary phase diagrams for Ti-Si-O compounds[66]47
Fig. 2-29 Ellingham diagram[67]48
Fig. 3-1 Schematic of MONOS device structure49
Fig. 3-2 Flow chart of experimental procedure of electrical measurement and material analysis50
Fig. 3-3 Schematic of ambient annealing system53
Fig. 3-4 Schematic drawing of PVD sputtering system55
Fig. 3-5 Sample structure used for electric measurement58
Fig. 3-6 Four-point probe59
Fig. 3-7 Alpha-step profilometry60
Fig. 3-8 Eillipsometer61
Fig. 3-9 Principle of X-ray photoelectron process63
Fig. 3-10 Connection condition for 4294A inside and outside dark box66
Fig. 4-1 HRTEM image of the stacking structure for TiO2 CTM (a) at 300000 magnification factor (b) at 800000 magnification73
Fig. 4-2 HRTEM image of the stacking structure for TiON CTM (a) at 300000 magnification factor (b) at 800000 amplification factor73
Fig. 4-3 EDS line-scan of the stacking structure for TiO2 CTM74
Fig. 4-4 EDS line-scan of the stacking structure for TiON CTM75
Fig. 4-5 XPS depth profiling of O 1s core levels of the SiO2/TiO2/SiO2/Si stack79
Fig. 4-6 XPS depth profiling of Ti 2p3/2 core levels of the SiO2/TiO2/SiO2/Si stack80
Fig. 4-7 XPS spectra of Ti 2p3/2 for the interface between charge trapping layer(TiO2) and tunneling layer(SiO2)80
Fig. 4-8 XPS spectra of O 1s for the interface between charge trapping layer(TiO2) and tunneling layer(SiO2)81
Fig. 4-9 XPS depth profiling of O 1s core levels of the SiO2/TiON/SiO2/Si stack81
Fig. 4-10 XPS depth profiling of Ti 2p3/2 core levels of the SiO2/TiON/SiO2/Si stack82
Fig. 4-11 XPS spectra of Ti 2p3/2 for the interface between charge trapping layer(TiON) and tunneling layer(SiO2)82
Fig. 4-12 XPS spectra of O 1s for the interface between charge trapping layer(TiON) and tunneling layer(SiO2)83
Fig. 4-13 XPS spectra of N 1s for the interface between charge trapping layer(TiON) and tunneling layer(SiO2)83
Fig. 4-14 C-V hysteresis after bidirectional voltage sweeping measured at 1MHz for the device for the device with TiO2 CTL86
Fig. 4-15 C-V hysteresis after bidirectional voltage sweeping measured at 1MHz for the device for the device with TiON CTL86
Fig. 4-16 C-V hysteresis after bidirectional voltage sweeping measured at 1MHz for the device for the device without CTL87
Fig. 4-17 C-V hysteresis window for devices with different CTL measured at 1MHz87
Fig. 4-18 Schematic band diagram of device with TiO2 CTL88
Fig. 4-19 Schematic band diagram of device with TiON CTL88
Fig. 4-20 C-V characteristics measured under different ranges of voltage at 1MHz for the device with TiON CTL92
Fig. 4-21 C-V characteristics measured under different ranges of voltage at 1MHz for the device with TiON CTL93
Fig. 4-22 C-V characteristics measured under different ranges of voltage at 1MHz for the device with TiON CTL94
Fig. 4-23 C-V characteristics measured under different ranges of voltage at 1MHz for the device with TiON CTL95
Fig. 4-24 Schematic band diagram of TiON CTM under the low programming voltage96
Fig. 4-25 Schematic band diagram of TiON CTM under the low erasing voltage96
Fig. 4-26 Schematic band diagram of TiON CTM under the high programming voltage97
Fig. 4-27 Schematic band diagram of TiON CTM under the high erasing voltage97
Fig. 4-28 P/E transient characteristics for devices with different CTL. The P/E gate voltage is ±15 V100
Fig. 4-29 Schematic band diagram of TiO2 CTM under the programming voltage of 15 V100
Fig. 4-30 Schematic band diagram of TiON CTM under the programming voltage of 15 V101
Fig. 4-31 Bidirectional C-V characteristics measured between +6 V and -6 V under different frequencies ranging from 1kHz to 1MHz for device with TiO2 CTL103
Fig. 4-32 Bidirectional C-V characteristics measured between +6 V and -6 V under different frequencies ranging from 1kHz to 1MHz for device with TiON CTL103
Fig. 4-33 VFB dependence on measuring frequency for devices with TiO2 or TiON CTL by C-V measurement analysis104
Fig. 4-34 D-V curves measured in the backward CV sweeping direction from 1MHz to 1kHz for TiO2 CTM104
Fig. 4-35 D-V curves measured in the backward CV sweeping direction from 1MHz to 1kHz for TiON CTM105
Fig. 4-36 Bidirectional C-V characteristics measured between +6 V and -6 V under different temperature ranging from 25℃ to 100℃ for device with TiO2 CTM107
Fig. 4-37 Bidirectional C-V characteristics measured between +6 V and -6 V under different temperature ranging from 25℃ to 100℃ for device with TiON CTM107
Fig. 4-38 D-V curves measured in the backward CV sweeping direction from 25℃ to 100℃ at 1MHz for TiO2 CTM108
Fig. 4-39 D-V curves measured in the backward CV sweeping direction from 25℃ to 100℃ at 1MHz for TiON CTM108
Fig. 4-40 Leakage current density versus gate voltage curves of the TiO2 CTM measured between +6 V and -6 V from 25℃ to 100℃110
Fig. 4-41 Leakage current density versus gate voltage curves of the TiON CTM measured between +6 V and -6 V from 25℃ to 100℃110
Fig. 4-42 The retention properties measured at elevated temperatures for the TiO2 and the TiON CTM113
Fig. 4-43 Relationship between ln(1/ΤT2) and 1/kT of the TiO2 CTM and the TiON CTM, where the slope of the fitting straight line represents the charge trarring energy level113
                                    

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