| 研究生: |
蔣宇睿 Chiang, Yih-Ray |
|---|---|
| 論文名稱: |
奈米尺度下之矽基電晶體先導性動態分析 Preliminary Dynamic Analysis of Nano-scale Silicon-based Transistors |
| 指導教授: |
蔡南全
Tsai, Nan-Chyuan |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 機械工程學系 Department of Mechanical Engineering |
| 論文出版年: | 2008 |
| 畢業學年度: | 96 |
| 語文別: | 中文 |
| 論文頁數: | 105 |
| 中文關鍵詞: | 次門檻擺幅 、量子傳輸 、電子態密度 、側壁空間形成法 |
| 外文關鍵詞: | Sidewall Spacer Formation, Sub-threshold Swing, Electron Density of State, Quantum Transport |
| 相關次數: | 點閱:98 下載:3 |
| 分享至: |
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本文目的在於探討電荷載子於奈米尺度下的運動特性,經由古典傳輸模型加入量子修正項後,可以得知量子傳輸特性與古典傳輸模型的差異。藉由商用軟體nanoMOS的模擬,可初步分析因晶體結構的改變或材料的選擇不同對奈米級導線場效電晶體的影響,如次門檻擺幅的上升和門檻電壓的下降等重要性能指標。另外,本研究亦使用VASP(Vienna ab initio Simulation Package)計算程式來初步模擬矽奈米線,藉由原子間的排列形成矽奈米線幾何截面與尺寸的不同設計,與摻雜元素取代晶體內的矽原子,進而得知奈米尺度下晶體的結構改變與電子態密度的分佈。模擬結果對日後奈米線電晶體在結構上的設計與元件材料的選擇提供了重要參考的依據。最後本文提出簡單易於實現的矽奈米線製程方法—側壁空間形成法(Sidewall Spacer Formation),以製造矽奈米線。
The goal of this thesis is aimed at the investigation upon the kinematic characteristics of the charge carriers within the silicon-based transistor under nano-scale effects, via classical transport model to include a quantum correction term so that the difference between quantum transport model and classical transport model can be unveiled. Based on the computer simulation of the commercial software nanoMOS, the impacts on nanowire field effect transistors due to various design of crystal structure and choice of doped material composition are analyzed. Conductance performance such as the sub-threshold swing and the threshold voltage are studied. Furthermore, this thesis utilizes software package VASP (Vienna ab initio Simulation Package) to simulate the behavior of the silicon-based nanowires by varying nanowires geometric cross-section and replacement of the silicon atoms in crystal by other elements, such that the induced distribution of the electron density of state of the nanowires owing to change of the crystal structure can be obtained. The simulation results provide essential basis for nanowires field effect transistor in structural design and potential choice of the device material for future developments. Finally, this thesis proposes a simple and easily realizable fabrication technique, sidewall spacer formation, for implementation of silicon nanowires.
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