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研究生: 黃詩喬
Huang, Shih-Chiao
論文名稱: 毫米波CMOS 低插入損耗變化之相移器及W- / K-band 射頻收發開關
Millimeter-Wave CMOS Low Insertion-Loss-Variation Phase Shifter and W- / K-band CMOS T/R Switches
指導教授: 莊惠如
Chuang, Huey-Ru
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 76
中文關鍵詞: 相移器射頻收發開關毫米波K與W頻段
外文關鍵詞: Phase Shifter (PS), T/R Switches, Millimeter-Wave (MMW), K / W-band
相關次數: 點閱:109下載:6
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  • 本論文研製毫米波CMOS低插入損耗變化相移器及W-與K-band 射頻收發開關。低插入損耗變化之相移器採用TSMC CMOS 0.18-μm製程,應用於天線陣列系統,其主要架構是在180°反射式相移器輸出串接一個可切換180°相位差之切換式相移器,藉由切換180°切換式相移器使整體相位達到360°連續可調控之特性。K-與W-band 射頻收發開關則是分別採用TSMC 0.18-μm和TSMC 90-nm GUTM CMOS製程來進行設計,在應用上開關電路主要是切換射頻前端收發機中發射端與接收端路徑。W-band (75 - 110 GHz) 開關在本論文中共有兩個電路,第一個電路主體使用串-並式開關架構並使用基極浮接技術(body-floating)來改善插入損耗與線性度,此外搭配並聯電感諧振及洩漏訊號消除技術改善其隔離度;第二個電路使用串-並式開關設計,串聯路徑上使用雙並聯路徑來作為設計主體,同時將匹配的傳輸線利用彎折的方式來達到微小化的作用,並搭配基極浮接技術、並聯諧振電感與疊接電晶體等技術來改善其開關特性。而在K-band (15 - 30 GHz)開關設計主要利用一縮小化的堆疊式電感概念,藉由此電感大幅縮減整體電路面積,以利於整合。電路皆使用Agilent ADS與Ansoft 3-D全波電磁模擬軟體HFSS來進行模擬,晶片量測部分則採fully on-wafer方式進行量測。

    This thesis presents the design of millimeter-wave (MMW) CMOS low-insertion loss phase shifters and W- / K-band CMOS T/R switches. The K-band phase shifter (PS) is fabricated using standard TSMC 0.18-μm CMOS technology. To achieve full 360° phase control, a (fixed) switch-type 180° phase shifter is applied to the continuous 180° reflection-type phase shifter for the phased-array antenna system. The K- and W-band T/R switches are fabricated using standard TSMC 0.18-μm and 90-nm GUTM CMOS technologies, respectively. The first W-band (75 - 110 GHz) switch is designed by using series-shunt structure with body-floating technique to improve the insertion loss and linearity performance. To enhance the isolation performance, the parallel inductor and leaking cancellation technique are adopted. The second W-band series-shunt type switch uses the double parallel-path structure. In addition, the body-floating, parallel inductor and stacked transistor techniques are used to improve the overall performance. In the K-band switch design, the chip size is much reduced by using the stacked inductor. All the measurements are performed by using the on-wafer measurement setup.

    第一章 緒論 1 1.1 研究動機與背景 1 1.2 論文架構 2 第二章 K-band全相位具低插入損耗變化之相移器 3 2.1 相移器簡介 3 2.2 常見可調式相移器架構 4 2.2.1 開關式相移器(switching type phase shifter, STPS) 5 2.2.2 向量調變式相移器(vector modulation phase shifter) 5 2.2.3 分佈式相移器(distributed phase shifter) 6 2.2.4 反射式相移器(reflection-type phase shifter, RTPS) 7 2.3 K-band全相位具低變化插入損耗之相移器 12 2.3.1 電路架構簡介 12 2.3.2 完整電路設計流程與考量 17 2.3.3 模擬與量測結果 18 2.3.4 結果與討論 22 第三章 W - band CMOS毫米波射頻收發開關 25 3.1 收發開關簡介 25 3.1.1 操作原理及重要參數介紹 25 3.1.2 電晶體開關模型 27 3.2 常見收發開關架構 29 3.2.1 串聯式(series type) 收發開關 30 3.2.2 串–並式(series-shunt type)收發開關 30 3.2.3 行進波 (traveling-wave) 概念之收發開關 31 3.2.4 非對稱型收發開關 31 3.3 改善收發開關特性之技術 32 3.3.1 疊接電晶體(stacked transistors)技術 32 3.3.2 並聯電感諧振式(shunt inductor resonance)收發開關[36][37] 33 3.3.3 基極浮接(body-floating)技術 33 3.3.4 洩漏訊號消除(leakage cancellation)技術 35 3.4 75 - 110 GHz CMOS高隔離度之射頻收發開關 36 3.4.1 電路架構簡介 36 3.4.2 電晶體尺寸選擇 37 3.4.3 使用隔離度改善技術之開關設計 38 3.4.4 完整電路設計流程與考量 39 3.4.5 模擬與量測結果 40 3.4.6 75 - 110 GHz CMOS高隔離度之射頻收發開關結果與討論 44 3.5 雙並聯路徑之75 - 110 GHz毫米波CMOS縮小化開關設計 46 3.5.1 電路架構簡介 47 3.5.2 完整電路設計流程與考量 48 3.5.3 模擬與量測結果 49 3.5.4 結果與討論 53 3.6 射頻收發開關設計總探討 55 3.6.1雙並聯路徑之75 - 110 GHz CMOS毫米波CMOS縮小化開關結果與討論 55 第四章 使用堆疊電感之縮小化15 - 30 GHz毫米波CMOS T/R開關 57 4.1 電路架構簡介 57 4.1.1 完整電路設計流程與考量 62 4.2 模擬與量測結果 63 4.3 結果與討論 67 第五章 結論 69 參考文獻 71

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