隨著摩爾定律快要走到盡頭，新的半導體製程與材料必須被開發與研究，鍺是非常有可能作為取代矽的材料，雖然成本較高，但其遷移率也較高，與矽的 CMOS製程也具兼容性，故鍺非常有希望作為未來技術節點的候選材料。
然而製作成元件後，遷移率會大大的下降，因為氧化層與半導體層之間的界面會因為懸浮鍵所形成的界面缺陷限制其良好的特性，故在這層界面的處裡上過去也過了廣泛的研究。
本實驗針對鍺鰭式電晶體先進行電性上的量測，發現當電壓正反掃時會有遲滯現象，再對元件照射紫外光一樣進行正反掃，遲滯現象會增加，因為照射紫外光的緣故會激發材料的電子電洞對，但激發出的載子並沒有流向汲極處，而是被界面處的陷阱困住或是氧化物內部的電荷包括製程上產生的與Band offset太低造成的載子穿隧，均會引發遲滯現象。
使用TCAD模擬軟體進行驗證，首先會先針對不同的尺寸模擬出理想狀況的電晶體特性，並且萃取電性參數作為指標，結果顯示出越小尺寸的元件在Ioff、DIBL與SS等負面參數上均較高，在物理上均非常符合，故可以先確認模擬的材料與結構具有優良的電晶體特性。再加入影響電晶體曲線的因素，包括漏電機制、溫度影響、Dit分佈與遷移率下降等因素進行調整，使模擬的曲線更接近量測結果。其中在Dit分佈上會先模擬在能隙上均勻分佈的狀況，藉此找尋適當的Dit分佈與濃度大小。另外當把midgap 或 donor-state 的Dit濃度增加會與量測元件照射紫外光曲線有相同的趨勢，因此驗證了當元件照射紫外光後在midgap 或 donor-state的Dit濃度增加。

As Moore's Law is coming to an end, new semiconductor processes and materials must be developed and researched. Germanium is very likely to be used as a material to replace silicon due to its higher mobility, though it comes with an expense of a comparatively higher cost. It is also compatible with the silicon CMOS process, so germanium is very promising as a candidate material for future technology nodes.
As the device is fabricated, the resultant mobility becomes greatly reduced due to a poor interface between the oxide layer and the semiconductor layer as a result of the dangling-bond-induced interfacial defects that limit the device performance. To mitigate these nagging issues, extensive research efforts have consistently been invested to formulate various avenues to curtail defect density.
In this experiment, the electrical measurement of the germanium FinFET is carried out, and it is found that hysteresis occurs when the forward and reverse voltages are swept. As the device is irradiated with ultraviolet light while performing a voltage sweep in both forward and reverse directions, the hysteresis becomes increasingly apparent. The foregoing observation is primarily attributed to the charges inside the oxide and the interfacial trapped defects.
TCAD simulation is also performed for verification. First, the ideal transistor characteristics are simulated to extract relevant electrical parameters when different device dimensions are taken into consideration. The results show that the relatively smaller devices do have higher negative parameters including Ioff, DIBL, and SS. The other factors that affect the transistor performance curves, including leakage mechanism, temperature influence, Dit distribution, and mobility reduction are also incorporated into the simulation model to closely match the simulated curves with the measurement results previously obtained. When the Dit concentration is increased in the midgap or donor-state, it has the same trend as that of the device irradiated with UV light.

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