本論文中，吾人研究改進薄膜電晶體的關鍵製程技術及結構，藉以提升元件特性以便應用於大面積平面顯示器。大面積平面顯示器的 薄膜電晶體要求速度快，漏電流少及體積小或全透明結構以提高開口 率( aperture ratio)。
為達到此目標，在傳統非晶矽薄膜電晶體中，吾人利用電漿輔助成長化學氣相沉積，堆疊製程方式及利用氫氣表面退成長出高品質的奈米矽晶薄膜，來增加元件移動率改善元件飽和電流及開關電流比。也運 用非n型高摻雜半導體層的最佳化雜質沉積，造成非晶矽與奈米矽之間 晶體結構的轉換，來降低n型高摻雜半導體層薄膜的電阻值。實驗證實此方式不僅優化了元件特性，亦提升了飽和電流(370%)也提升了開關比(1515%)。
此外，更進一步選用非晶氧化銦鎵鋅(Indium gallium zinc oxide, IGZO) 這種新材料來進一步提升元件速率及透明度特性。我們首先使用IGZO 單 通道/單閘極絕縁的下閘極 全透明薄膜電晶體的結構 ，透過阻值分析、拉曼光譜分析(Raman)、傅立葉轉換紅外線光譜儀(FTIP)、成份分析 (EDS)、掃描式電子顯微鏡(SEM)、X-光繞射儀(XRD)、原子力顯微鏡(AFM)等技術來分析薄膜並利用HP4156C半導體參數分析儀/光譜儀 (UV/VIS/NIR spectrometer)量測研究元件電特性及透明度。
接著 ，更增加了通道緩衝層 ( Channel buffer Layer) 及閘極絕縁阻檔層( Gate dielectric barrier )作成IGZO 雙通道/雙閘極絕縁的下閘極全透明薄膜電晶體。實驗顯示，比起單通道/單閘極絕縁者，此結構約可提升3次方的開 關電流比，減 少 800 倍 的漏 電 流，透 光 度 也 由 84%改善到 86.4 %,如 此使元件更適合大面積的運用。

另 外，值 得 一 提的 是，在論文中，吾人除了研發各種薄膜電晶體的關鍵製程技及結構外，也同時對這些關鍵製程技術及結構改善薄膜電晶體性能的機制與理論 ， 配合簡明圖式作詳盡的說明。

Generally, the thin film transistor (TFT) for a large panel should have the characteristics of high channel mobility, large on-current and low leakage. Besides, it also needs small size and high transparence to attain high aperture ratio. To match these requirements, in this thesis, we studied the novel technologies to promote conventional a-Si TFT performances and use of indium gallium zinc oxide (IGZO) instead of a-Si as active layer to enhance channel mobility and device transparence.
In the conventional a-Si TFT, first, we optimized the phosphorus (P) doping concentration in the source / drain (S/D) n+ layer to transfer the deposited Si film from an amorphous structure to the nano one, thus achieving the lowest S/D contact resistance .As a result, both on-current and on/off current ratio were improved up to 370% and 1515 %, respectively.
Next, we employed the layer by layer technology with a hot wire chemical vapor deposition system (HWCVD) to directly deposit high quality nano-Si film , and then used a post hydrogen anneal (PHA) to treat the film surface. The experimental results showed that the PHA could improve (about 10%) both saturation and off currents. Especially for a multilayer channel structure, the improvement became more obviously.

Furthermore, the high performance amorphous InGaZnO full transparent thin film transistors (TTFT) with both single and double channel were prepared on glass substrate and studied in details. In the double channel TTFT, the rapid thermal annealed ZnO was added as the second channel and used to buffer the InGaZnO deposition. Besides, we used the Al2O3 as the HfO2 gate dielectric barrier to lower gate leakage. As a result, both technologies promote ~ 3 orders in on/off current ratio and reduce leakages current ~ 800 times, and improve the average transparence from 84% to 86.4 % in the range of 500nm-800nm wavelengths.
In the thesis, except the novel technologies studies, we also investigate these improvement origins and illustrate them in details with the comprehensive the schematic diagrams.

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