| 研究生: |
莊景翔 Chuang, Ching-Hsiang |
|---|---|
| 論文名稱: |
系統層軟體模擬於硬體實作之漸近式驗證應用於H.264 Main Profile解碼器 System Level Software Simulation for Hardware Implementation and its Incremental Verification with Application to H.264 Main Profile Decoder |
| 指導教授: |
蘇文鈺
Su, W. Y. |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 75 |
| 中文關鍵詞: | 軟體模擬 、漸近式驗證 、H.264 Main Profile解碼器 、FPGA模擬器 、系統層 |
| 外文關鍵詞: | FPGA Simulator, Incremental Verification, System Level, H.264 Main Profile Decoder, Software Simulation |
| 相關次數: | 點閱:90 下載:1 |
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近年來,隨著電子設計輔助工具(EDA Tools)的進步,大大改變電路設計的方式。如今撰寫電路,已經如同撰寫軟體一般,可以使用程式語言去描述,如Verilog與VHDL。這使得軟體開發者,也可以很輕易地入門電路設計。
電路設計完成之後,如同軟體設計,也要經過測試與除錯。但是與軟體不同的是,傳統驗證電路的方式,非常沒有效率。原因除了HDL(Hardware Description Language)模擬器模擬速度不快之外,最主要的就是缺乏系統與電路二位一體的開發概念。一個電路設計,當它實際應用於某個系統之上時,問題的尋找將更為容易,而且直接影響除錯的效率。
本論文以軟體開發者的角度觀察設計硬體的流程,著重於電路與系統的整合。論文中以系統角度進行電路設計,提出以系統層軟體模擬的方式輔助硬體設計之初步構想,並且企圖整合高效能的HDL模擬器 – FPGA取代傳統HDL模擬器,以增進模擬之效率。帶來以軟體系統為主體之硬體開發流程。
論文中提供一軟體模擬平台之實作範例,並且將之實際運用於H.264 Main Profile解碼器之硬體開發。
In recent years, EDA tools are getting more and more powerful, and have greatly changed the ways of circuit design. Today, doing a circuit design is nothing more than programming. Circuit designers can turn into software programmers if they use C/C++ or other programming languages. Oppositely, software programmers can get involved into circuit design very quickly if they are eager to learn another programming language which is hardware description languages – HDL( Verilog or VHDL).
Just like software development, the works after the implementation of circuit are testing and debugging. The verification efficiency of circuit design is worst than software because of the slow speed of HDL simulator. However, the major problem of traditional ways of circuit design is taking system integration and circuit design apart. A circuit designer may never know how to integrate his circuit into a system or how his circuit works on the system. System integration helps discover more bugs and defects and also provides a great testing environment for circuit verification to increase the efficiency of removing bugs and defects.
In this thesis, we act as software developers and put more concentrations on the integration of system and circuits. In order to do the circuit design in system level, we have developed a system level simulation platform which is fully written in C++. For the sake of making HDL simulation faster, a FPGA simulator is introduced. Now we are doing circuit design under the proposed system simulation platform which makes verification more efficient than before.
Finally, we provide a reference design of system simulation platform, and we also apply it on the implementation of H.264 Main Profile decoder.
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