簡易檢索 / 詳目顯示

研究生: 莊景翔
Chuang, Ching-Hsiang
論文名稱: 系統層軟體模擬於硬體實作之漸近式驗證應用於H.264 Main Profile解碼器
System Level Software Simulation for Hardware Implementation and its Incremental Verification with Application to H.264 Main Profile Decoder
指導教授: 蘇文鈺
Su, W. Y.
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 75
中文關鍵詞: 軟體模擬漸近式驗證H.264 Main Profile解碼器FPGA模擬器系統層
外文關鍵詞: FPGA Simulator, Incremental Verification, System Level, H.264 Main Profile Decoder, Software Simulation
相關次數: 點閱:90下載:1
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近年來,隨著電子設計輔助工具(EDA Tools)的進步,大大改變電路設計的方式。如今撰寫電路,已經如同撰寫軟體一般,可以使用程式語言去描述,如Verilog與VHDL。這使得軟體開發者,也可以很輕易地入門電路設計。
    電路設計完成之後,如同軟體設計,也要經過測試與除錯。但是與軟體不同的是,傳統驗證電路的方式,非常沒有效率。原因除了HDL(Hardware Description Language)模擬器模擬速度不快之外,最主要的就是缺乏系統與電路二位一體的開發概念。一個電路設計,當它實際應用於某個系統之上時,問題的尋找將更為容易,而且直接影響除錯的效率。
    本論文以軟體開發者的角度觀察設計硬體的流程,著重於電路與系統的整合。論文中以系統角度進行電路設計,提出以系統層軟體模擬的方式輔助硬體設計之初步構想,並且企圖整合高效能的HDL模擬器 – FPGA取代傳統HDL模擬器,以增進模擬之效率。帶來以軟體系統為主體之硬體開發流程。
    論文中提供一軟體模擬平台之實作範例,並且將之實際運用於H.264 Main Profile解碼器之硬體開發。

    In recent years, EDA tools are getting more and more powerful, and have greatly changed the ways of circuit design. Today, doing a circuit design is nothing more than programming. Circuit designers can turn into software programmers if they use C/C++ or other programming languages. Oppositely, software programmers can get involved into circuit design very quickly if they are eager to learn another programming language which is hardware description languages – HDL( Verilog or VHDL).
    Just like software development, the works after the implementation of circuit are testing and debugging. The verification efficiency of circuit design is worst than software because of the slow speed of HDL simulator. However, the major problem of traditional ways of circuit design is taking system integration and circuit design apart. A circuit designer may never know how to integrate his circuit into a system or how his circuit works on the system. System integration helps discover more bugs and defects and also provides a great testing environment for circuit verification to increase the efficiency of removing bugs and defects.
    In this thesis, we act as software developers and put more concentrations on the integration of system and circuits. In order to do the circuit design in system level, we have developed a system level simulation platform which is fully written in C++. For the sake of making HDL simulation faster, a FPGA simulator is introduced. Now we are doing circuit design under the proposed system simulation platform which makes verification more efficient than before.
    Finally, we provide a reference design of system simulation platform, and we also apply it on the implementation of H.264 Main Profile decoder.

    摘要 I ABSTRACT II 誌謝 IV 目錄 V 表目錄 VII 圖目錄 VIII 【第一章】 序論 1 1.1 背景與動機 1 【第二章】 系統層軟體模擬於硬體實作 3 2.1 系統層建立抽象化模型 5 2.2 由抽象化模型產生的設計規格實作Soft IP 7 2.3利用抽象化模型驗證Soft IP 8 【第三章】 整合軟體模擬與硬體之開發流程 及漸近式驗證 9 3.1 整合軟體模擬與硬體之開發流程 10 3.2 使用FPGA作為硬體模擬器 11 3.3 驗證上之優勢 14 3.3.1 硬體單元測試(Unit Testing) 17 3.3.2 系統層硬體漸近式驗證 17 3.3.3 抽象模型與電路模擬器協同工作 18 3.4 除錯上之優勢 20 3.4.1 純軟體  模擬硬體之軟體 21 3.4.2 模擬硬體之軟體  純硬體 21 3.4.3 產生硬體測試資料 21 3.4.3.1單純Inputs/Outputs 22 3.4.3.2產生Testbench 23 【第四章】 應用實例-H.264 MAIN PROFILE解碼器 24 4.1 簡介H.264解碼器與設定實作目標 24 4.1.1 解碼器實作目標 25 4.1.2 串流格式 26 4.1.3 解碼器運作流程 27 4.1.4 開發使用工具列表 29 4.2 開始建置系統層模擬環境 30 4.2.1 使用C++建立模擬環境 32 4.2.2 模組間之溝通介面 – Bus 35 4.2.3 Master與Slave 38 4.2.3.1 (Master)–SCREAM RISC32 Instruction Simulator 39 4.2.3.2 (Slave)–32-bit memory model 40 4.2.3.3 (Slave)–File Source 41 4.2.3.4 (Slave)–Pixel Buffer 42 4.2.3.5 (Master/Slave)–DMA 43 4.2.3.6 (Master)–Bus Interface 44 4.2.3.7 (Slave)–AVC Decoder Core 44 4.2.4 模擬平台測試範例 – YUV Player 45 4.2.4.1 Scenario 1 (RISC32+FileSrc+Pixbuf) 45 4.2.4.1 Scenario 2 (RISC32+FileSrc+Pixbuf+RAM32+DMA) 47 4.3 實作H.264 Main Profile解碼器 48 4.3.1 ITIQ engine 48 4.3.2 Intra-prediction engine 50 4.3.2.a Intra4x4/16x16/8x8 prediction 51 4.3.2.b MPM derivation 52 4.3.2.c Intra-MB Controller 53 4.3.4 Inter-prediction engine 54 4.3.4.a MVP Derivation 55 4.3.4.b MC與WP-default WP 57 4.3.4.c 4x4-block based Inter-Prediction controller 58 4.4 實驗結果 59 4.4.1 軟體H.264解碼器 60 4.4.2 I-Frame取代成硬體的H.264解碼器 61 【第五章】 結論與未來展望 63 5.1 結論 63 5.2 未來展望 65 參考資料 67 附錄A H.264 PROFILES與LEVELS 70 附錄B – TBGEN.PY 73 附錄C – MKGEN.PY 74 自述 75

    [1] Electronic System Level [Online]. Available: http://en.wikipedia.org/wiki/Electronic_system_level
    [2] RealView SoC Designer [Online]. Available: http://www.arm.com/products/DevTools/SoCDesigner.html
    [3] CoWare The ESL Leader [Online]. Available: http://www.coware.com/
    [4] Synopsys System-Level Solutions [Online]. Available: http://www.synopsys.com/products/designware/sls.html
    [5] Mentor Graphics Electronic System Level Design [Online]. Available: http://www.mentor.com/products/esl/
    [6] OSCI. SystemC Community [Online]. Available: http://www.systemc.org/
    [7] SMIMS FPGA發展平台 [Onine]. Available: http://www.smims.com/index_big5.html
    [8] IEEE Standards Board, "IEEE Standard for Software Unit Testing: An American National Standard, ANSI/IEEE Std 1008-1987" in IEEE Standards: Software Engineering, Volume Two: Process Standards; 1999 Edition; published by The Institute of Electrical and Electronics Engineers, Inc. Software Engineering Technical Committee of the IEEE Computer Society.
    [9] Microsoft Visual Studio Home. MSDN [Online]. Available: http://msdn2.microsoft.com/zh-tw/vstudio/default.aspx
    [10] GDB: The GNU Project Debugger [Online]. Available: http://sourceware.org/gdb/
    [11] HumphreyS. Watts. “PSP – a self-improvement process for software engineers”, Pearson Education, Inc., 2005.
    [12] ITU, ITU-T Reconmmendation H.264(03/2005)
    [13] ThomasWiegand, Gary J. Sullivan, Senior Member, IEEE, Gisle Bjontegaard, and Ajay Luthra, Senior Member, IEEE, “Overview of the H.264/AVC Video Coding Standard”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [14] Iain E G Richardson, "H.264 / MPEG-4 Part 10 : Variable Length Coding", Vcodex H.264 Tutorial
    [15] Iain E G Richardson, "H.264 / MPEG-4 Part 10 : Transform & Quantization", Vcodex H.264 Tutorial
    [16] Iain E G Richardson, "H.264 / MPEG-4 Part 10 : Intra Prediction", Vcodex H.264 Tutorial
    [17] Iain E G Richardson, "H.264 / MPEG-4 Part 10 : Inter Prediction", Vcodex H.264 Tutorial
    [18] Iain E G Richardson, "H.264 / MPEG-4 Part 10 : Introduction to CABAC", Vcodex H.264 Tutorial
    [19] Iain E G Richardson, "Frame and picture management", Vcodex H.264 Tutorial
    [20] Stephan Wenger, “H.264/AVC Over IP”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [21] Michael Horowitz, Anthony Joch, Faouzi Kossentini, Senior Member, IEEE, and Antti Hallapuro, “H.264/AVC Baseline Profile Decoder Complexity Analysis”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [22] Ville Lappalainen, Antti Hallapuro, and Timo D. Hämäläinen, ” Complexity of Optimized H.26L Video Decoder Implementation”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [23] Markus Flierl, Student Member, IEEE and Bernd Girod, Fellow, IEEE, “Generalized B Pictures and the Draft H.264/AVCVideo-Compression Standard”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [24] Peter List, Anthony Joch, Jani Lainema, Gisle Bjøntegaard, and Marta Karczewicz, “Adaptive Deblocking Filter”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003
    [25] H.264/AVC JM Reference Software [Online]. Available: http://iphome.hhi.de/suehring/tml/
    [26] GCC, the GNU Compiler Collection [Online]. Available: http://gcc.gnu.org/
    [27] Valgrind Home [Online]. Available: http://valgrind.org/
    [28] Altera. Quartus II Software [Online]. Available: http://www.altera.com/products/software/products/quartus2/qts-index.html
    [29] ISO, “Programming languages — C++”, ISO/IEC 14882
    [30] gtkmm, C++ Interfaces for GTK+ and GNOME [Online]. Available: http://www.gtkmm.org/
    [31] Grady Booch, James Rumbaugh, Ivar Jacobson, “The Unified Modeling Language User Guide”, Addison Wesley 1998
    [32] Martin Fowler, “UML Distilled: A Brief Guide to the Standard Object Modeling Language, Third Edition”, Addison Wesley 2003
    [33] Eric GammaHelm, Ralph Johnson, John VlissidesRichard. “Design Patterns: Elements of Reusable Object-Oriented Software”, Addison-Wesley, 1995.
    [34] 陳忠和, “SCREAM RISC32 Instruction Simulator (SystemC model)”
    [35] Ubuntu Linux [Online]. Available: http://www.ubuntu.com/
    [36] Yu-Hui Su, “A Progressive Design Flow and Its Application to H.264 BP RDO Encoder VLSI Design”, National Cheng Kung University Master thesis, 2006
    [37] Chang-Peng Wang, “An Architecture Design of De-blocking Filter in H.264/AVC for Real-time High Definition Video Processing”, National Cheng Kung University Master thesis, 2006

    下載圖示 校內:2009-09-11公開
    校外:2009-09-11公開
    QR CODE