| 研究生: |
陳信禕 Chen, Hsin-Yi |
|---|---|
| 論文名稱: |
應用於Ka頻段之氮化鎵寬頻功率放大器積體電路設計與性能優化之研究 Research of Design and Performance Optimization for GaN-Based Wideband Power Amplifier Integrated Circuit operating at Ka-Band |
| 指導教授: |
王永和
Wang, Yeong-Her |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2025 |
| 畢業學年度: | 113 |
| 語文別: | 英文 |
| 論文頁數: | 147 |
| 中文關鍵詞: | 射頻功率放大器 、無線通訊發射端 、單晶微波積體電路 、氮化鎵製成 、Ka 頻段 、Class AB 、寬頻 、功率合併 |
| 外文關鍵詞: | Radio Frequency Power Amplifier, Wireless Communication Transmitter, Monolithic Microwave Integrated Circuit (MMIC), AlGaN/GaN HEMT process, Ka-band, Class AB, Broadband, Power combing |
| 相關次數: | 點閱:51 下載:0 |
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本論文旨在研究無線通訊發射機系統中的功率放大器。射頻功率放大器為提升輸入訊號之功率以利後續應用。本論文使用穩懋GaN-based HEMT製成實現操作在Ka頻段之射頻功率放大器。論文第一部分為兩顆Ka頻段1W功率放大器設計,第一顆設計使用穩懋GaN 0.25um HEMT製成,設計採兩級Class AB架構,使用傳輸線與MIM電容配合史密斯圖設計匹配網路,採用LPF架構作為主要架構。量測結果可以在26 GHz實現24 dBm輸出功率,與小訊號增益11.08 dB。
第二顆設計使用穩懋GaN 0.12um HEMT製成,輸出匹配網路改成使用二階BPF架構,使其操作頻寬相對於前次設計來的更充裕。另外在中間級匹配改善前次設計過於複雜的路徑,使用直接匹配的方式降低損耗。量測結果在S參數部分有著插入損耗19.5 dB,輸出反射損耗-8 dB與輸入反射損耗-14 dB。而大訊號量測方面,在操作頻率為28 GHz時可以達到31.5 dBm最大輸出功率,PAE達到33 %以及小訊號增益19.5 dB。在整體操作頻段27~29.5 GHz也有著不錯的特性表現。
論文第二部分為使用功率合併技術實現Ka頻段2W功率放大器設計。此設計使用穩懋GaN 0.12um HEMT製成進行製作。輸出級設計結合功率合併電路與改良式BPF架構讓整體功率放大器電路進一步提升輸出功率表現來到約35 dBm,同時還能維持著PAE約33 %,與小訊號增益約22 dB。在晶片面積上僅使用了2.15*1.1 mm2 ,整體功率密度達到1.343 W/mm2 。
This thesis aims to study power amplifiers in wireless communication transmitter systems. RF power amplifiers are used to enhance the power of input signals for subsequent applications. In this thesis, a Ka-band RF power amplifier was realized using WIN Semiconductors' GaN-based HEMT process.
The first part of the thesis involves the design of two 1W Ka-band power amplifiers. The first design employs WIN's GaN 0.25µm HEMT process, featuring a two-stage Class AB architecture. Matching networks were designed using transmission lines and MIM capacitors in conjunction with Smith charts, and an LPF architecture was adopted as the primary structure. Measurement results demonstrate an output power of 24 dBm at 26 GHz, with a small signal gain of 11.08 dB.
The second design uses WIN's GaN 0.12µm HEMT process, with the output matching network replaced by a second-order BPF structure, providing a wider operating bandwidth than the previous design. Additionally, the intermediate matching network was simplified to reduce loss by adopting a direct matching approach, addressing the complexity in the earlier design. Measured S-parameters indicate an insertion loss of 19.5 dB, output return loss of -8 dB, and input return loss of -14 dB. The design achieves a maximum output power of 31.5 dBm, a PAE of 33%, and a small-signal gain of 19.5 dB at 28 GHz for large-signal measurements. The design exhibits excellent performance characteristics across the 27–29.5 GHz operating band.
The second part of the thesis focuses on the design of a 2W Ka-band power amplifier using power combining techniques. This design was fabricated with WIN's GaN 0.12µm HEMT process. The output stage integrates a power combining circuit and an improved BPF structure to enhance overall output power performance, achieving nearly 35 dBm while maintaining a PAE of approximately 33 % and a small signal gain of around 22 dB. The chip occupies an area of just 2.15 × 1.1 mm², achieving a power density of 1.343 W/mm².
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校內:2030-02-06公開