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研究生：	蘇正建 Su, Cheng-Chien
論文名稱：	高效能的封包處理平行架構 Efficient Parallel Architecture for Packet Processing with Hardware Support
指導教授：	張燕光 Chang, Yeim-Kuan
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	91
中文關鍵詞：	路由表查詢、封包分類、深度封包檢測、三元內容定址記憶體
外文關鍵詞：	IP Lookup, Packet classification, Deep packet inspection, TCAM
相關次數：	點閱：115 下載：2
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今日，高速網際網路的實現，爆炸性成長的網路流量需要高速的路由器來支援。交換器及路由器需要提供網路封包傳輸，服務質量，入侵偵測等功能才能應付大量的網際網路應用程式。高性能的網路裝置為了能夠處理這些封包通常會有三個重要的技術，包含封包傳送，封包分類，深層封包檢測。傳統的網路設備都是通用處理器架構再利用軟體演算法去提供這三個重要的技術。但封包的大量成長使用傳統的路由器所提供的流量是不夠理想的。為了滿足大量的封包處理目前最使用的架構是平行化的封包處理架構。平行化的封包處理架構通常使用多核心網路處理器、元件可程式邏輯閘陣列和三位元內容定址記憶體。
本論文著重在使用元件可程式邏輯閘陣列和三位元內容定址記憶體提供一個平行處理封包的架構。FPGA 提供了可程式化的硬體平台，可以在上面發展平行化的封包處理架構。TCAM 是一種特殊的記憶體，它可以提供了平行搜尋的能力，只需要一次的系統週期內即可平行比對完成TCAM 內的所有資料。FPGA 和TCAM 有可以平行比對、容易使用及快速處理的優點，然而，它們的售價卻是昂貴的。在論文中我們針對封包分類及深層封包檢測提出了一個平行處理的架構並實作在FPGA 的平台上。我們所提的架構可以有效率的使用FPGA 內的邏輯元件，且在封包分類上可以達到超過100Gbps，在深度封包檢測上達到7.27Gpbs 的傳輸速率。在TCAM 上，我們找到了一個壓縮TCAM 資料的新方法，比之前的相關壓縮方法更能夠節省TCAM 空間。最後我們也提供一個在封包傳送時可同時使用多顆TCAM 的平行架構，改善了只單顆TCAM 搜尋的速度。

In today's era of high-speed Internet, explosive traffic growth requires the support of high-performance switches and routers. Switches and routers provide the functionalities of packet switching, quality service differentiation, and network security for managing various Internet applications. High-performance network devices for dealing with these packets typically require three important technologies: packet forwarding, packet classification, and deep packet inspection. Traditional network devices use general-purpose processor architectures and software algorithms to procure these three technologies. However, the massive growth of packet traffic renders traditional network devices dissatisfactory. Often, parallel architectures provide feasible solutions for processing packets in massive quantities. Parallel packet processing architectures typically use multi-core network processors, field programmable gate arrays (FPGAs), and ternary content addressable memory (TCAM) for implementation. In this thesis, we focus on FPGA and TCAM to support efficient parallel packet processing. FPGA offers a programmable hardware platform that can develop a parallel packet processing architecture. TCAM is a special memory that can compare in parallel input data with all entries of TCAM in one lookup time. FPGA and TCAM offer the advantages of a high degree of parallelism, easy configuration, and fast processing time. Nevertheless, these are expensive hardware devices. In this thesis, we propose two parallel architectures for packet classification and deep packet inspection, and implement them in FPGA. Our architectures efficiently use the logic cell of FPGA, achieving throughput of over 100 Gbps and 7.27 Gbps for packet classification and deep packet inspection, respectively. We present TCAM compression schemes for packet classification and deep packet inspection. Our proposed compression schemes significantly reduce the number of TCAM entries, allowing TCAM to store a greater amount of data compared with a previous work. Finally, we propose a parallel multiple TCAM architecture for packet forwarding, which can further improve the single TCAM architecture.

Chapter 1 Introduction.................................................................... 1
Chapter 2 Background...................................................................... 4
1 Packet Forwarding Problem Statement................................................... 4
2 Packet Classification Problem Statement............................................... 6
3 Deep Packet Inspection Problem Statement.............................................. 6
4 Field Programmable Gate Array ........................................................ 8
5 Ternary Content Addressable Memory (TCAM)............................................. 9
Chapter 3 Design Contention Resolver for TCAM-based Parallel Architecture ................11
1 Introduction .........................................................................11
2 Proposed Contention Resolver Design...................................................14
Chapter 4 Efficient TCAM Encoding Schemes for Packet Classification using the Gray Code...16
1 Introduction .........................................................................16
2 Preliminaries and Related Work........................................................19
2.1 Direct range-to-prefix conversion ..................................................20
2.2 Elementary interval-based encoding scheme ..........................................20
2.3 Parallel packet classification encoding (PPCE) scheme ..............................21
3 Proposed Range Encoding Schemes ......................................................23
3.1 Elementary interval and BRGC-based range encoding...................................24
3.2 Enhancing PPCE with BRGC ...........................................................24
3.3 Many-to-one code assignment ........................................................29
3.4 One-to-many code assignment ........................................................29
4 Performance Evaluation ...............................................................30
5 Conclusions ..........................................................................32
Chapter 5 High-speed and Memory-efficient Pipeline Architecture for Packet Classification.33
1 Introduction .........................................................................33
2 Related Work..........................................................................34
3 Proposed Schemes......................................................................36
3.1 Set Pruning Multi-bit Trie .........................................................37
3.2 Partitioning by Wildcards (PW) .....................................................38
3.3 Partitioning by Lengths (PL)........................................................39
4 Implementation........................................................................41
5 Performance ..........................................................................43
6 Conclusion............................................................................44
Chapter 6 Cost-effective Pre-processing-based NFA Pattern Matching Architecture for NIDS..45
1 Introduction .........................................................................45
2 Related Work..........................................................................46
3 Proposed Scheme ......................................................................50
4 Proposed Architecture in FPGA.........................................................53
4.1 Detailed Design of the Pre-process Module...........................................55
4.2 False Positive of the Pro-process Module ...........................................57
5 Performance Evaluation ...............................................................59
6 Conclusion............................................................................62
Chapter 7 Efficient Deterministic Finite Automata in TCAM for Deep Packet Inspection......63
1 Introduction .........................................................................63
2 Related Work..........................................................................64
2.1 Famous Software-based Approaches ...................................................64
2.2 Deterministic Finite Automaton .....................................................65
2.3 Ternary String and TCAM-based Solutions ............................................67
3 Proposed DFA in TCAM..................................................................68
3.1 Motivation .........................................................................68
3.2 Problem Statement and Preliminaries ................................................69
3.3 Group DFA states ...................................................................71
3.4 Independent Symbol Encoding (ISE) Scheme ...........................................71
3.5 Disjoint Set Encoding (DSE) Scheme..................................................74
4 Performance Evaluation ...............................................................77
5 Conclusion............................................................................78
Chapter 8 Conclusions and Future Work ....................................................79
References ...............................................................................82
Publication Lists ........................................................................90
                                    

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