在本論文中，我們提出幾種可以有效提升奈米金氧半電晶體元件特性的新穎奈米製程，包括新穎的淺溝槽隔離 (STI) 蝕刻、微小顆粒矽閘極低溫沉積、後氮化極超薄氧化層退火、及使用碳離子佈植法來改善極超淺接面特性等。首先我們使用自動化變圓（rounding）的方法改善淺溝槽隔離的上角落，藉以消除反窄寬度效應 (INWE) 及改善窄寬度元件的特性。實驗證實本法可以增加了8%的飽和電流，簡化達到平均溝槽深度的蝕刻步驟及擴大蝕刻的製程寬度（process window）。也達到了降低成本的目的。最重要的是，此法既不傷害閘極氧化層的統整性，也不會增加接面漏電流。
在極超薄氧化層的應用上，我們使用低溫 (705 oC -715 oC) 並精準地控制反應氣體流量和壓力來沈積具微小顆粒的多晶矽閘極。因顆粒很微小故可消除或避免顆粒突入薄氧化層。如此一來，可得到平順的矽閘極/氧化層介面，而達到降低閘極漏電流。元件的趨動飽和電流在n型及p型也因而分別增加了9%、7%。
此外，吾人也利用高溫後氮化超薄氧化層退火(post-nitridation annealing) 來改善奈米金氧半電晶體元件的特性。當退火的溫度由1000 oC 提高到1050 oC，可使n型奈米金氧半電晶體之趨動飽和電流增加7.9%，閘極之漏電流降低了3.81%；p型奈米金氧半電晶體趨動飽和電流驟增16.7% ，閘極漏電流降低了4.31%。這些顯著的特性增進，證實高溫的氮化氧化層退火的確可改善氮化氧化層／矽介面狀態，以及增加了閘極氧化層電性厚度。
在n型奈米金氧半電晶體的極超淺接面的特性改善方面，我們使用碳離子群束佈植法，並藉著碳離子群束在矽中產生拉緊變形（strain）來增加載子移動性。因此放置碳離子群束在矽中的取代點 (substitutional site)位置是非常重要的。但在n型慘雜時也需要磷去佔據矽中的取代點。於是形成了碳與磷佔據取代點的競爭。也因此造成佈植的活化和拉緊變形之間的取捨。我們研究最佳化的磷和碳分子各種佈植範圍及快閃式退火技術參數來產生低阻值，高拉緊變形的極超淺接面，和無缺陷矽碳層。透過阻值、二次離子質譜儀 (SIMS) 、穿透式電子顯微鏡 (TEM) 、高解析度XRD (HRXRD)等量測技術，來分析矽碳層在極超淺接面的特性。實驗證實最佳化的製程可有效地增加趨動飽和電流約4.7%，並且減少缺陷引發的瞬間增益擴散 (TED)，以及良好的短通道效應控制。吾人更以不　同圖形模式來解說其中原理。

This dissertation presents various skills; including a new STI (shallow trench isolation) etch method, small grain size with low temperature polygen process, post-nitridation annealing (PNA) and the carbon co-implant to promote nano CMOS device performances. First, we use automatically top corner rounding (ATCR) STI etch to improve CMOS narrow width device performances. Compared to the conventional methods, the ATCR could increase 8% of the driving current (Idsat) together in a unit process step, thus getting easy process control and cost down benefits. Additionally, the ATCR has a wider process window. Besides, the technique does not degrade the gate oxide integrity, and junction leakage current.
Next, we reduce the grain size of poly Si gate by lowering deposition temperature to achieve low sub-threshold leakage and gate leakage. This is due to the smaller grain size can offer a smoother interface to an ultra-thin gate oxide than a big one. Besides, the driving currents are also respectively increased ~9% and ~7% for n- and p- MOSFETs, as the temperatures are lowered from 715oC to 705oC. The most importance is that the small grain size does not degrade the gate oxide integrity and device junction leakage current.
Additionally, used a high temperature post-nitridation annealing (PNA) to improve nano devices with pulsed radio frequency decoupled plasma nitrided ultra-thin (< 50Å) gate dielectric. Results indicate that for a n-type MOSFET, as the PNA temperature rising from 1000oC to 1050oC, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT.
In final, a new molecular carbon co-implant technique was developed. The introduction of carbon ions induces the tensile strain to enhance the mobility. We optimized the dose and energy ranges for both P and C implants along with some anneal parameters to produce low sheet resistance (Rs) and high tensile strain. Besides, Rs measurement, SIMS, XTEM and HRXRD techniques were employed to characterize the doped layer. The optimized implants effectively improved 55nm n-MOSFET performances with Idsat 4.7% gain and significantly reduced transient enhanced diffusion (TED) due to the formation of SiC complex to sink Si interstitials.

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