本篇論文討論深次微米互補式金氧半電晶體之製程技術中，製程影響閘極氧化層與金屬導線可靠性的研究及模式。第一部份、閘極氧化層沉積前及沉積後製程對元件的可靠性影響，第二部份、金屬導線中失效機制的可靠性研究及模式：其中包含鈷化金屬（Co salicide）的形成、雙鑲嵌銅導線的電子遷移、鎢插塞（W-plug）通道於鋁銅合金導線中的腐蝕現象以及銅導線於低介電係數（low-k）介質層製程所產生的金屬腐蝕缺陷。
在第一部份主要討論閘極氧化層的可靠性問題。首先，吾人提出在金氧半（MOS）電晶體中因小於2 奈米極薄厚度的閘極氧化層(gate oxide) 所呈現的異常電容-電壓（C-V）特性曲線之模式。將MOS中源極與汲極不接地來量測電容-電壓特性曲線，當強反轉發生時，只出現高頻的C-V特性曲線。反之，若將源極與汲極接地，則只呈現低頻的C-V 特性曲線。接著，吾人提出在深次微米互補式金氧半電晶體 (CMOS) 之製程技術中，gate oxide沉積前的清洗製程對電晶體元件的表現以及對閘極氧化層強化性（GOI）損壞的影響。經由實驗分析以及量測結果可知，以熱的去離子水來做晶片清洗，通道表面上所產生的細微粗糙度及應力，將使得GOI降低並導致電晶體元件的特性（飽和電流、起始電壓、漏電率等）分布變化更大。除此之外，吾人亦提出另一種於多晶矽閘極（Poly gate）成型後因晶片清洗所產生的可靠性問題。例如，在一般晶舟浸潤式的溼式化學清洗槽中，以去離子水來清除附著於晶片表面上的化學物質時會使用較強的沖洗力道，因而可能造成Poly gate的破壞，進而產生可靠性的問題。本篇論文提供了一個好的方法既在晶片清洗過程中可藉由適當的沖洗力道強弱的調整來控制去除雜質（Particle）的效率，並且找出減少Poly gate被破壞的方案來發展晶片清洗的製程技術，給未來先進的奈米製程技術作為參考。
第二部份主要討論是金屬導線的可靠性問題。首先研究的是Co salicide導線的應力效應。於Co salicide 的製程中，導線的阻值會隨著不同環繞結構所產生的應力而有所變化，此應力的大小及方向性對於鈷原子的擴散、Co salicide的厚度、及矽化金屬的形狀，皆有著極大的影響。此研究在對於深次微米CMOS製程技術中，應力效應對Co salicide導線阻值的影響，提供了相當有價值的資訊。
此外，本論文也研究雙鑲嵌銅製程中因介質孔側壁（Via sidewall）所影響的電子遷移（electromigration）。在銅導線中因Via sidewall導致的電子遷移失效機制，主要是由於介質孔側壁間不平衡的熱應力、銅與氮化鉭（TaN）間的熱膨脹、及氮化鉭的表面（例如表面粗糙度與晶格大小的效應）所引起。為了對這些因素作更詳細的研究與鑑定，吾人利用穿透式電子顯微鏡（TEM）、場發射掃描式電子顯微鏡（FESEM）、與原子力顯微鏡（AFM）的量測結果來輔助說明。另外由實驗結果証明，可藉由提高TaN阻障（barrier）的階梯覆蓋率（step coverage）來增強銅製程中電子遷移的性能。吾人並建議於深次微技術中，將此step coverage列為重要的製程整合主題。
另一個由製程所導致內連線的可靠度問題，吾人發現是起始於鋁金屬應用的鎢插塞（W-plug）所發生的腐蝕現象。在鋁金屬導線製程中，鎢是被使用為介質孔洞的填充物，在伴隨著虛擬金屬刻線（dummy metal）的介質孔串(via chains)中，其具有較高的介質孔開路故障率。經過乾式蝕刻製程後，可以明顯發現正電荷殘留在虛擬金屬刻線上，進而引起電場的產生，並與隨後的聚合物濕式剝除製程產生電化學反應，而提高鎢插塞的分解。為了減低介質孔開路故障發生率，可利用增長通入氮氣（N2）或氬氣（Argon）的製程時間來消除靜電，或利用水蒸氣亦可完全消除介質孔的開路故障。因此吾人認為在鋁金屬導線的技術中，鎢插塞的腐蝕主要是由dummy metal 放電效應所支配。
最後是以探討銅導線邊緣的腐蝕缺陷做為金屬導線的可靠性問題之研究。在以碳基氧化矽（SiOC）為low-k介電質層的雙鑲嵌銅製程中，隨著銅化學機械平坦化（Cu CMP）製程之延遲時間的增加，所引起的銅線邊緣腐蝕缺陷比起以氟矽玻璃（FSG）為常見的介電層，較為明顯增加。吾人利用接觸角水滴實驗來檢測，顯示水滴於碳基氧化矽表面的接觸角(θ)大於在氟矽玻璃上。因為low-k介電質材料擁有斥水性（hydrophobic）特性，因而產生較強的表面張力，並將化學機械研磨液（CMP slurry）中的過氧化氫（H2O2）分子推向銅線邊緣，因此發生邊緣腐蝕缺陷之現象高於在氟矽玻璃材料上。根據接觸角實驗及SEM的分析結果證實，因low-k碳基氧化矽的斥水特性，於Cu CMP製程中slurry的H2O2分子累積而造成銅導線的邊緣腐蝕缺陷。

This dissertation investigates how the pre and post gate oxide processes affect the reliability of 1) gate oxide, and, more importantly, 2) failure mechanisms of interconnect reliability in deep submicron CMOS technology, i.e., cobalt salicide formation, electromigration of Cu dual damascene, corrosions of tungsten plug (W-plug) in Al metallization and Cu line in low-k dielectric, respectively.
The first part of this study focuses on the gate oxide reliability. To begin, I will report the modeling of abnormal capacitance-voltage (C-V) characteristics found in MOS transistors with ultra-thin gate oxide less than 2.0 nm. The abnormal features of the measured C-V curves in strongly inversion state include both high frequency styles without source/drain (S/D) connected to ground, and lower frequency styles with S/D connected to ground. After describing the model, I will discuss the impacts on devices performance and gate oxide integrity (GOI) degradation, caused by the pre-gate oxide clean process in deep submicron CMOS technology. Our analysis shows that the GOI degradation, which causes a large fluctuation of devices performance (like Isat, Vt, leakage current, etc.), is attributable to the channel surface micro-roughness and stress generated from hot de-ionized (DI) water clean. In addition to the pre gate oxide process, the wafer clean process after patterning poly gate electrode introduces additional reliability issues. For example, the physical forces, originated from high shower flow rate in a typical immersion of cassettes of wafers into wet chemical cleaning baths, cause the poly-line damages during DI water flushing for adhesion chemical removal. However, since the correction of damages may affect particle removal efficiency, the physical forces should be properly tuned. We think this study offers good methods to develop wafer-cleaning process for future advanced nanometer CMOS technology.
The second part of this dissertation focuses on interconnect reliability. This part begins with the study of resistance variations of cobalt (Co) salicide interconnect, which is caused by different stresses in surrounding structures. During the salicidation processes, these stress levels induce diffusion of Co atoms and thus salicide thickness, and forms of Co salicide layer. This study offers valuable information for the studies of stress-induced effects on Co salicide resistance in deep submicron CMOS technology.
The study of interconnect reliability continues with a systematic discussion on the electromigration (EM) failure in via sidewall for Cu dual damascene process. The failure mechanisms are caused by the unbalance thermal stress, thermal expansion between copper and TaN, and TaN surface morphology (e.g. surface roughness and grain size effects). These factors were investigated and evaluated in details through transmission microscope, field emission scanning electronic microscope, and AFM. Moreover, I will give an experiment resulting that the enhancement of step coverage of TaN barrier layer to prolong the EM lifetime, and suggest that the step coverage of TaN barrier layer becomes an important integration subject for sub-0.13μm and beyond technologies.
Another interconnect reliability relates to the process induced W-plug corrosion from Al metallization applications. Since the W is used as filling material of via holes in Al interconnect, the via chains with dummy metal have a higher via-open failure rate than those without. The failure is due to the positive charges remained on dummy metal after metal dry etch process, which induces an electrical field to enhance the electrochemical reaction of dissolving W-plug in the followed polymer wet strip process. To eliminate failure, we need to bear in mind that the cumulative percentage of nominal via resistance decreases with increasing de-chuck process time for both N2 and argon. That is, when H2O vapor ambient is used, via resistance failures will be eliminated. Therefore, this part shows that the dummy metal charging effect dominates the W-plug corrosion in Al metallization technology.
The study of interconnect reliability concludes with a discussion on Cu line edge corrosion in the low-k dielectric layer, the damage caused by H2O2 from a certain Cu CMP process idle time. A simulated process using water droplet indicates that the contact angle (θ) of the water droplet placed on low-k SiOC (64.6°) is larger than that of FSG (52.7°) at the initial instant contact. The difference in angle is due to hydrophobic characteristic of low-k dielectric, which induces a high surface tension. This in turn pushes the H2O2 molecules contained in CMP slurry toward the edge of the Cu line, thus resulting in a greater corrosive reaction than FSG. The contact angle measurements and additional SEM analysis further confirm that the Cu line edge corrosion is attributable to the accumulation of the H2O2 molecules from CMP slurry because of the hydrophobic property of low-k SiOC film.

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