此論文針對不同條件的介面處理，探討對高介電係數介電層與矽鍺介面的影 響。與眾多文獻的比較，可以發現大多數矽鍺電容的介電層都很厚大於 5 奈米，隨著介電 層厚度減少，矽鍺介面的品質提高，且電性表現漸漸優化。而此論文為了在追求更小的 EOT， 介電層厚度約 3 奈米，若要有優良的的特性表現，對於矽鍺介面的品質要求更高，所以 在製程中使用較薄的氮化鋁、氮化鉿來優化。這兩種材料可以使矽鍺電容有很低的漏電，使 因磊晶上去而較不穩定的矽鍺降低他的漏電，且經過一連串快速熱退火和微波退火的條件 測試，而取得最佳的結果去做鰭式電晶體，然而電容在微波退火後(3.5p，100 秒)後， 電性上顯示有較小的遲滯現象(約123.66 mV)與等效電容厚度(1.78 奈米)，且閘極漏 電流在閘極電壓為-1 V 時，約為 1.05×10-4 A/cm2，最後成功應用在鰭式電晶體中。

In this paper, the interface processing under different conditions discusses the influence on the interface between the high-k dielectric layer and the SiGe interface. Compared with many literatures, it can be found that the dielectric layer of most silicon-germanium capacitors is thicker than 5 nm. As the thickness of the dielectric layer decreases, the quality of the silicon-germanium interface improves, and the electrical performance is gradually optimized. In this paper, in order to pursue a smaller EOT, the thickness of the dielectric layer is about 3 nanometers. In order to have excellent performance, the quality of the silicon-germanium interface is higher, so thinner AlN and HfN are used in the process. These two materials can make silicon germanium capacitors have very low leakage, so that silicon germanium, which is more unstable due to epitaxial deposition, can reduce its leakage. After a series of rapid thermal annealing and microwave annealing tests, the best results were obtained. The result is to do a fin transistor, but the capacitor after microwave annealing (3.5p, 100 seconds), the TiN/ZrO2/HfN/SiGe/Si MOSCAP shows a small C-V hysteresis loop of ~123.66 mV and low capacitance equivalent thickness (CET) of 1.78 nm, and leakage current density (Jg) of ~1.05×10-4 A/cm2 at a gate bias of Vg = -1.0 V. Then, performing on FinFETs.

[1] C. D. Young, "Enabling Semiconductor Innovation and Growth-EUV lithography drives Moore's law well into the next decade," in APAC TMT Conference, Taipei, Taiwan, March 14, 2018 2018.
[2] D. A. Neamen, Semiconductor physics and devices: basic principles. New York, NY: McGraw-Hill, 2012.
[3] V. Chan et al., "High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering," in IEEE International Electron Devices Meeting 2003, 2003: IEEE, pp. 3.8. 1-3.8. 4.
[4] Nawaz, M., On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs. Active and Passive Electronic Components, 2015. 2015: p. 1-12.
[5] Toriumi, A., et al., Opportunities and challenges for Ge CMOS–Control of interfacing field on Ge is a key. Microelectronic Engineering, 2009. 86(7-9): p. 1571-1576.
[6] Wang, S.K., et al., Desorption kinetics of GeO from GeO 2/Ge structure. Journal of applied physics, 2010. 108(5): p. 054104.
[7] Signamarcheix, T., et al., Germanium oxynitride (Ge O x N y) as a back interface passivation layer for Germanium-on-insulator substrates. Applied Physics Letters, 2008. 93(2): p. 022109.
[8] Kutsuki, K., et al., Thermal robustness and improved electrical properties of ultrathin germanium oxynitride gate dielectric. Japanese Journal of Applied Physics, 2011. 50(1R): p. 010106.
[9] Watanabe, H., et al. High-quality GeON gate dielectrics formed by plasma nitridation of ultrathin thermal oxides on Ge (100). in 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. 2010. IEEE.
[10] JER-HUEIH CHEN, J., et al., Ultrathin Al2O3 and HfO2 gate dielectrics on surface-nitrided Ge. IEEE transactions on electron devices, 2004. 51(9): p. 1441-1447. [11] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256-268, 1974.
[12] S. M. Sze and K. K. Ng, Physics of semiconductor devices. John wiley & sons, 2006.
[13] H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's," IEEE Transactions on electron devices, vol. 30, no. 10, pp. 1244-1251, 1983.
[14] C. A. Mack, "Fifty years of Moore's law," IEEE Transactions on semiconductor manufacturing, vol. 24, no. 2, pp. 202-207, 2011.
[15] M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, and M. Ohwada, "Growth of native oxide on a silicon surface," Journal of Applied Physics, vol. 68, no. 3, pp. 1272-1281, 1990.
[16] T. Irisawa et al., "High-performance uniaxially strained SiGe-on-insulator pMOSFETs fabricated by lateral-strain-relaxation technique," IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2809-2815, 2006.
[17] L. Yang et al., "Si/SiGe heterostructure parameters for device simulations,"
Semiconductor Science and Technology, vol. 19, no. 10, p. 1174, 2004.
[18] O. Weber et al., "Examination of additive mobility enhancements for uniaxial stress combined with biaxially strained Si, biaxially strained SiGe and Ge channel MOSFETs," in 2007 IEEE International Electron Devices Meeting, 2007: IEEE, pp. 719-722.
[19] W. Cheng, A. Teramoto, M. Hirayama, S. Sugawa, and T. Ohmi, "Impact of improved high-performance Si (110)-oriented metal–oxide–semiconductor field-effect transistors using accumulation-mode fully depleted silicon-on-insulator devices," Japanese journal of applied physics, vol. 45, no. 4S, p. 3110, 2006.
[20] Y. Song et al., "Performance breakthrough in gate-all-around nanowire n-and p-type MOSFETs fabricated on bulk silicon substrate," IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1885-1890, 2012.
[21] K. J. Kuhn, "CMOS scaling beyond 32nm: Challenges and opportunities," in Proceedings of the 46th Annual Design Automation Conference, 2009: ACM, pp. 310- 313.
[22] X. Huang et al., "Sub-50 nm P-channel FinFET," IEEE Transactions on Electron Devices, vol. 48, no. 5, pp. 880-886, 2001.
[23] I. Vurgaftman, J. á. Meyer, and L. á. Ram-Mohan, "Band parameters for III–V compound semiconductors and their alloys," Journal of applied physics, vol. 89, no. 11, pp. 5815-5875, 2001.
[24] I. Ferain, C. A. Colinge, and J.-P. Colinge, "Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors," Nature, vol. 479, no. 7373, p. 310, 2011.
[25] Wei-Li Lee, et al. "Improving Interface State Density and Thermal Stability of High-κ Gate Stack Through High-Vacuum Annealing on Si0.5Ge0.5" IEEE Electron Device Letters, Vol. 40, 2019, DOI: 10.1109/LED.2019.2905139.
[26] M. Zhao, et al. "Isotopic labeling study of the oxygen diffusion in HfO2/SiO2/Si," Appl. Phys. Lett.,Vol. 90, 2007, DOI: 10.1063/1.2717539
[27] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, "Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics," IEEE Electron Device Lett., Vol. 24, no. 2, pp. 87–89, Feb. 2003.
[28] K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, and J. W. Maes, "The mechanism of mobility degradation in MISFETs with Al2O3 gate dielectric," VLSI Symp. Tech. Dig., pp. 188–189, 2002.
[29] L. M. Terman, "An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes," Solid-State Electronics. Vol. 5, p.285, 1962, DOI: 10.1016/0038-1101(62)90111- 9.
[30] N. M. Johnson, D. K. Biegelsen, M. D. Moyer, S. T. Chang, E. H. Poindexter, and P. J. Caplan, "Characteristic electronic defects at the Si‐SiO2 interface," Appl. Phys. Lett., Vol. 43, p.563, 1983, DOI: 10.1063/1.94420.
[31] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. DE Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, Vol. 31, p.42, 1984, DOI: 10.1109/T-ED.1984.21472.
[32] J. R. Brews, "Rapid interface parameterization using a single MOS conductance curve," Solid-State Electron, Vol. 26, p.711,1983, 10.1016/0038-1101(83)90030-8.
[33] W. A. Hill and C. C. Coleman, "A single-frequency approximation for interface-state density determination," Solid State Electron, Vol. 23, p.987, 1980, DOI: 10.1016/0038-1101(80)90064-7.
[34] S. Jakschik, A. Avellan, U. Schroeder, and J. W. Bartha, "Influence of Al2O3 dielectrics on the trap-depth profiles in MOS devices investigated by the charge-pumping method," IEEE Trans. Electron Devices, Vol. 51, no. 12, pp. 2252–2255, Dec. 2004.
[35] R. E. Paulsen, R. R. Siergiej, M. L. French, and M. H. White, "Observation of near-interface oxide traps with the charge-pumping technique," IEEE Electron Device Lett., Vol. 13, no. 12, pp. 627–629, Dec. 1992.
[36] R. E. Paulsen and M. H. White, "Theory and application of charge pumping for the characterization of Si−SiO2 interface and near- interface oxide traps," IEEE Trans. Electron Devices, Vol. 41, no. 7, pp. 1213–1216, Jul. 1994.
[37] B. Djezzar, A. Smatti, and S. Qussalah, "A new oxide-trap based on charge-pumping (OTCP) extraction method for irradiated MOSFET device: Part II (Low Frequencies)," IEEE Trans. Nucl. Sci., Vol. 51, no. 4, pp. 1732–1736, Aug. 2004.
[38] Chun-Yuan Lu, Kuei-Shu Chang-Liao, Chun-Chang Lu, Ping-Hung Tsai, and Tien-Ko Wang, "Detection of Border Trap Density and Energy Distribution Along the Gate Dielectric Bulk of High-κ Gated MOS Devices," IEEE Electron Device Letter, VOL. 28, NO. 5, pp.432-435, MAY 2007.
[39] S. Christensson, I. Lundstrom, and C. Svensson, "Low frequency noise in MOS transistors—I Theory," Solid-State Electron. Vol.11, p.797, 1968, DOI: 10.1016/0038-1101(68)90100-7.
[40] Wu W.-H., Tsui B.-Y., Chen M.-C., Hou Y.-T., Jin Y., Tao H.-J., Chen S.-C. and Liang M.-S., " Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-? gate stack by low- frequency capacitance-voltage measurement," Appl. Phys. Lett. Vol. p.89, 2006, DOI: 10.1063/1.2364064.
[41] NIST XPS database https://srdata.nist.gov/xps/ [42] Y. Liu et al., "Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication," IEEE transactions on nanotechnology, vol. 5, no. 6, pp. 723-730, 2006.
[43] K. Endo et al., "Variability analysis of TiN metal-gate FinFETs," IEEE Electron Device Letters, vol. 31, no. 6, pp. 546-548, 2010.
[44] W. L. Kalb and B. Batlogg, "Calculating the trap density of states in organic field-effect transistors from experiment: A comparison of different methods," physical review B, vol. 81, no. 3, p. 035327, 2010.
[45] R. Winter, J. Ahn, P. C. McIntyre, and M. Eizenberg, "New method for determining flat-band voltage in high mobility semiconductors," Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 31, no. 3, p. 030604, 2013.
[46] W. C. Lee, C. J. Cho, J.-H. Choi, J. D. Song, C. S. Hwang, and S. K. Kim, "Correct extraction of frequency dispersion in accumulation capacitance in InGaAs metal- insulator-semiconductor devices," Electronic Materials Letters, vol. 12, no. 6, pp. 768- 772, 2016.
[47] J. Lin et al., "An investigation of capacitance-voltage hysteresis in metal/high-k/In0. 53Ga0. 47As metal-oxide-semiconductor capacitors," Journal of Applied Physics, vol. 114, no. 14, p. 144105, 2013.
[48] J. Franco et al., "SiGe channel technology: Superior reliability toward ultrathin EOT devices—Part I: NBTI," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 396-404, 2012.
[49] K. Sardashti et al., "Nitride passivation of the interface between high-k dielectrics and SiGe," Applied Physics Letters, vol. 108, no. 1, p. 011604, 2016.
[50] T. Yu, C. Jin, Y. Yang, L. Zhuge, X. Wu, and Z. Wu, "Effect of NH3 plasma treatment on the interfacial property between ultrathin HfO2 and strained Si0. 65Ge0. 35 substrate," Journal of Applied Physics, vol. 113, no. 4, p. 044105, 2013.
[51] S. Wang, J. Chai, J. Pan, and A. Huan, "Thermal stability and band alignments for Ge 3 N 4 dielectrics on Ge," Applied physics letters, vol. 89, no. 2, p. 022105, 2006.