本論文中，探討了四種相異之製程，有著不同輕摻雜區蝕刻深度的高壓金氧半場效電晶體(HV-MOSFETs)之特性，包括特性與串聯電阻(Rs)之相關性以及元件受到熱載子注入影響所產生的電性退化現象及其元件生命週期之完整議題。
首先，介紹高壓金氧半場效電晶體元件其優點特色與實際在市場中的應用。接下來陳述研究之動機，對於四種不同輕摻雜區蝕刻深度之高壓金氧半電晶體相互比較下，元件生命週期有所差異之現象，對其延伸之研究。本論文中亦有介紹熱載子效應及其與元件可靠度之關係、以及分析元件特性之電腦輔助設計(TCAD)模擬軟體。
作完基礎簡介之後，呈現本研究中使用元件之間的製程差異，並且闡述元件結構以及量測設定與方法，其中包含：元件電流ID-VD 、線性區電流ID-VG與基板電流Isub-VG之量測。
本研究之內容，探討了相異製程元件其輕摻雜區之串聯電阻值，與各種電性萃取參數之相關性。文中先敘述了各種電性參數之萃取方法，並且呈現實驗量測之數據結果，再以元件的串聯電阻值對基板電流等參數做出相關性圖，再使用電腦輔助設計(TCAD)模擬軟體校對量測結果，並進一步模擬研究出造成這些相關性趨勢之原因。如基板電流隨串聯電阻增加而呈現減少趨勢，是因為產生基板電流之衝擊離子化效應(Impact Ionization)，主要即發生在輕摻雜區，因此將受串聯電阻變動所影響。
此外，本研究之另一重點為探討元件之熱載子可靠度，主要觀察發現輕摻雜區蝕刻深度較淺之高壓金氧半場效電晶體之元件，在元件生命週期此一方面，相較於輕摻雜區蝕刻深度較深的高壓金氧半場效電晶體，有較良好的可靠度特性。最後佐以電腦輔助設計(TCAD)模擬軟體分析並發現造成元件可靠度差異之原因為元件電場與電流分布之不同，此結果對於未來製造高壓金氧半場效電晶體元件的研究得以有更多的參考。

In the thesis, different processes manufactured high voltage metal-oxide-semiconductor field effect transistors (HV-MOSFET) with various Si recess depth are investigated. These devices’ series resistance (Rs) correlation and hot-carrier-induced degradation were compared with each other. The different device lifetime and mechanisms between the devices was studied.
First, we illustrate the advantages and the applications of HV-MOSFET. Then we present the motivation of further studying high-voltage device with different processes. Because of the fact that high voltage devices with lower Si recess depth had better hot-carrier reliability comparing with device with higher Si recess depth. Thus, the relationship between hot carrier injection (HCI) and device reliability are performed in the thesis. Moreover, technology computer aid design (TCAD) was used to analyze the details of the devices.
The differential between high-voltage devices with various Si recess structure are presented in the second part of the thesis, and the structure of the devices and the measurement methodology and setup are described as well. Including device current ID-VD, linear region current ID-VG and substrate current Isub-VG.
The main part of the thesis is focused in part three and part four. In part three, the correlation of Rs in devices with different processes is investigated. the extraction methodology of various device characteristics and correlation plot were presented. After that, TCAD simulation software is utilized to confirm the measurement data and explain the phenomenon of Rs correlation.
The hot-carrier reliability issue was discussed in part four, The measurement setup and stress condition are presented. Then we illustrate the results of hot-carrier stress test. Subsequently, TCAD was utilized to analyze the mechanism between these four devices, for instance, the electric field contour, impact ionization rate contour and current flowlines contour. At the end, we find that both vertical electric field and current flowlines are the reason why device with higher Si recess depth and lower substrate current has higher degradation rate. Our research results can be used in application to predict the reliability of high-voltage devices with Si recess structure.

[1] Y. Shi, N. Feilchenfeld, R. Phelps, M. Levy, M. Knaipp and R. Minixhofer, “Drift Design Impact on Quasi-Saturation & HCI for Scalable N-LDMOS”, IEEE International Symposium on Power Semiconductor Devices & IC's, San Diego, 2011, pp.215~218
[2] N. Klein, S. Levin, G. Fleishon, S. Levy, A. Eyal, and S. Shapira, “Device design tradeoffs for 55v LDMOS driver embedded in 0.18 micronplatform”, IEEE 25th Convention of Electrical and Electronics Engineers in Israel, 2008, pp. 736~740
[3] Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and Mike King, “Design and Characterization of Submicron BiCMOS Compatible High-Voltage NMOS and PMOS Devices,” IEEE Transactions on Electron Devices, 1997, vol.44, no.2, pp. 331~338
[4] B. S. Doyle and K. R. Mistry, "Anomalous Hot-Carrier Behavior for LDD p-Channel Transistors" IEEE Electron Device Letters, 1993, vol.14, no.11
[5] M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. PageÁs and S. Merchant, “A new lateral power MOSFET for smart power ICs: the ``LUDMOS concept'”, Microelectronics Journal, 1999, vol.30, no.6, pp. 551~561
[6] Y. C. Liang, S. Xu, C. Ren, P. D. Foo, “New partial SOI LDMOS device with high power-added efficiency for 2 GHz RF power amplifier applications”, 26th Annual Confjerence of the IEEE, 2000, vol.2, pp.1001~1006
[7] S. Ogura, P. J. Tsang, W.W. Walker, D.L. Critchlow and J.F. Shepard, “Elimination of hot electron gate current by the lightly doped drain-source structure,” IEEE Electron Devices Meeting, International, 1981, vol.27, pp.651~654
[8] H. Mikoshiba, T Horiuchi and K. Hamano, “Comparison of Drain Structures in n-Channel MOSFET’s,” IEEE Transactions on Electron Devices, 1986, vol.ED-33, no. 1, pp.140~144
[9] J. F. Chen, K, M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin and S. L. Hsu "Characteristics and Improvement in Hot-Carrier Reliability of Sub-Micrometer High-Voltage Double Diffused Drain Metal–Oxide–Semiconductor Field-Effect Transistors" Japanese Journal of Applied Physics, 2007, vol.46, no.4B, pp.2019~2022
[10] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Shih and K. Wu "An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors" IEEE Transactions on Device and Materials Reliability, 2009, vol.9, no.3
[11] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu "Mechanisms of Hot-Carrier-Induced Threshold-Voltage Shift in High-Voltage p-Type LDMOS Transistors" IEEE Transactions on Electron Devices, 2009, vol. 56, no. 12
[12] C. R. Yan, J. F. Chen, C. Y. Lin, "Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide" Japanese Journal of Applied Physics, 2013, 04CC07
[13] J. F. Chen, T. H. Chen and D. R. Ai “Two-stage hot-carrier-induced degradation of p-type LDMOS transistors” IEEE Electronics Letters, 2014, vol.50, no.23, pp.1751~1753
[14] K. Eriguchi, A. Matsuda, Y. Nakakubo, M. Kamei, H. Ohta, K. Ono, “Study of plasma-induced “Si recess structure” and its effects on threshold voltage variability in advanced MOSFETs” 2009 IEEE International Conference on IC Design and Technology, 2009, pp.101~104
[15] E. Steven, "The Emerging Enernet: Convergence of the Smart Grid with the Internet of Things", Rural Electric Power Conference (REPC), 2015 IEEE, 2015, pp.65~68
[16] L. Coetzee, J. Eksteen "The Internet of Things - promise for the future? An introduction" IST-Africa Conference Proceedings, 2011, vol.2, pp.240~247
[17] A. M. Gamundani, "An impact review on internet of things attacks" Emerging Trends in Networks and Computer Communications (ETNCC),2015, pp.114~118
[18] Silicon Wafer:
http://cdn.wccftech.com/wp-content/uploads/2014/03/2x-nm-wafer.jpg
[19] Home Electronics:
http://luminanceav.com/images/Home_electronics.png
[20] Apple products:
https://www.apple.com
[21] Samsung video wall:
http://p.globalsources.com/IMAGES/PDT/B1134990462/2x2-42-inch-Full-HD-LED-Video-Wall.jpg
[22] ARM - Internet of things:
http://www.arm.com/zh/markets/internet-of-things-iot.php
[23] JR East Company – North Land Shinkansen:
http://www.jreast.co.jp/tc/routemaps/hokurikushinkansen.html
[24]Boeing Airplane: http://mymahoganymodel.com/images_solo/Boeing-787-9-Dreamliner-House-Colors-Version-2-M3-4.jpg
[25] Automobile Electronics(Audi R8):
http://images.carandbike.com/car-images/big/audi/r8/audi-r8.jpg?v=3
[26] High Voltage MOSFET Technology, Models, and Applications Vaidyanathan Subramanian, PhD 200mm Foundry Enablement. IBM Systems and Technology Group (STG)
[27] K. Bae, M. Jin, H. Lim, L. Hwang, D. Shin, J. Park, J. Heo, J. Lee, J. Do, I. Bae, C. Jeon and J. Park, “Behaviors and physical degradation of HfSiON MOSFET linked to strained CESL performance booster”, Reliability Physics Symposium (IRPS), 2011 IEEE International, 2011, pp.PL.1.1~PL.1.5
[28] C. M. Hu, C. T. Simon, H. Fu-Chieh, P. K. ko, T. Y. Chan and K. W. Terrill “Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE Journal of Solid-State Circuits, 1985, pp.295~305
[29] A. Duncan, U. Ravaioli, J. Jakumeit, "Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors" IEEE Transactions on Electron Devices, vol.45, pp.867~876
[30] R, Arora, E. Fleetwood, E. X. Zhang, N. E. Lourenco, J. D. Cressler, D. M. Fleetwood, R. D. Schrimpf, A. K. Sutton, G. Freeman, B. Greene "Impact of Technology Scaling in sub-100 nm nMOSFETs on Total-Dose Radiation Response and Hot-Carrier Reliability" IEEE Transactions on Nuclear Science, vol.61, pp.1426~1432
[31] S. R. Banna, P. C. H. Chan, M. Chan, P. K. Ko "Impact of scaling silicon film thickness on hot carrier effects in thin film fully depleted SOI MOSFETs" Device Research Conference, 1996. Digest. 54th Annual, 1996, pp.112~113
[32] C. Chen, Z. Liu, T. P. Ma, "Analysis of enhanced hot-carrier effects in scaled flash memory devices" IEEE Transactions on Electron Devices, vol.45, pp.1524~1530
[33] R. Woltjer, G. M. Paulzen, P. H. Woerlec, C. A. H. Juffermans, H. Lifka "Hot-carrier experiments on scaled NMOS transistors" ESSDERC '90: 20th European Solid State Device Research Conference, 1990, pp.249~252
[34] Silvaco “TCAD World Leader” Silvaco engineered excellence.
[35]Agilent Technologies, B1500A semiconductor device analysis introduction:
https://www.testworld.com/used-electronic-test-equipment/keysight-agilent-parametric-test-systems/keysight-agilent-b1500a-semiconductor-device-parameter-analyzer-characterization-system-mainframe-easyexpert/
[36] M. M. Lunenborg, H. C. de Graaff, A. J. Mouthaan, J. F. Verweij "Anomalous NMOSFET Substrate Current Behavior at Accelerated Hot-Carrier Stress Conditions" Solid State Device Research Conference, 1995
[37] E, E. King, R. C. Lacoe and J. W. Ratkovic "The Role of the Spacer Oxide in Determining Worst-case Hot-Carrier Stress Conditions for NMOS LDD Devices", IEEE 38"Annual International Reliability Physics Symposium, 2000
[38] Swin Super Solution & Service:
http://www.3-.com.tw/fengxi/front/bin/ptdetail.phtml?Part=darkbox&Category=40
[39] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Lee, T. Y. Huang, C. M. Liu and S. L. Hsu, "An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistors" Japanese Journal of Applied Physics, 2008, vol. 47, no.4, pp.2641~2644
[40] S. Xu, Y. Zhu, P. D. Foo, Y. C. Liang and J. K. O. Sin, "Folded Gate LDMOS with Low On-Resistance and High Transconductance" ISPSD’2000, 2000
[41] J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu and C. M. Liu "Mechanism and Modeling of On-Resistance Degradation in n-Type Lateral Diffused Metal-Oxide-Semiconductor Transistors" Japanese Journal of Applied Physics, 2009, vol.48, 04C040
[42] J. F. Chen, C. P. Chang, Y. M. Liu, Y. L. Tsai, H. T. Hsu, C. Y. Chen and H. P. Hwang, "Drift Region Doping Effects on Characteristics and Reliability of High-Voltage n-Type Metal-Oxide-Semiconductor Transistors" Japanese Journal of Applied Physics, 2016, vol.55, 01AD03
[43] "Guide to using TCAD with examples",2009, Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2, Santa Clara, CA 95054
[44] "Athena User’s Manual", 2013, Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2, Santa Clara, CA 95054
[45] "Atlas User Manual - DEVICE SIMULATION SOFTWARE", 2013, Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2, Santa Clara, CA 95054