目前廣為應用的非晶矽薄膜電晶體雖然製程簡單可以大面積低溫均勻成長，但其載子場效遷移率太低導致驅動電流較低是其最大的缺點。雖然近來積極研究的多晶矽薄膜電晶體擁有大的驅動電流，但因其需高溫製程故不利於玻璃基板上成長。此外，大面積低溫沉積的多晶矽則製程繁雜，不易均勻成長且具較高成本。奈米晶矽薄膜電晶體，不但保有目前非晶矽薄膜技術的優點可以在低溫(<250℃)下大面積及高速率成長，最重要的是其具有較高載子場效遷移率以提升驅動電流及增加開關電流比。
本論文利用具有高沉積速率與低成長溫度優點的熱鎢絲化學氣相沉積(HWCVD)技術來成長奈米晶矽薄膜，並以場發射掃瞄式電子顯微鏡(FESEM)、原子力顯微鏡(AFM)、X光繞射儀(XRD)、傅立葉轉換紅外線光譜儀(FTIR)和電流-電壓曲線量測來分析薄膜各種參數，如：薄膜厚度、熱退火處理、有無添加緩衝層和不同電極對薄膜電特性的影響。此外，我們並以最佳薄膜參數研製出各種不同結構的奈米晶矽薄膜電晶體，如：改變絕緣層厚度、有無添加緩衝層、不同層數的主動層疊層技術及採用不同n+層結構。成長出的最佳元件特性為：最低關電流為6.3×10-11(A)、最高開電流為2.5×10-5(A)、最大開關電流比為~106和最佳漂移遷移率為18.58(cm2/Vs)。

Nanocrystalline silicon (nc-Si) film has higher mobility than amorphous silicon film to elevate the current driving ability and can be uniformly deposited at low temperature (250℃), thus was employed to prepare thin film transistor (TFT) for large area display applications.
In this work, the hot-wire chemical vapor deposition (HWCVD) was used to prepare TFT for its feature of low temperature and high deposition rate. We analyzed the influence of deposition conditions such as film thickness, with and without a buffer layer, and thermal annealing on characteristics of the film through FESEM, AFM, XRD, FTIR, and I-V curve measurements. Besides, we successfully fabricate the high performance nc-Si TFTs with various structure such as different gate oxide thicknesses, with and without a buffer layer, various layer number for the layer-by-layer process, and different n+ layer structures. The best performance of the developed nc-Si TFT are 6.3×10-11 (A) for leakage current, 2.5×10-5 (A) for device driving on current, ~106 for on/off current ratio , and 18.58 (cm2/Vs) for drift mobility.

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