在醫學內視鏡攝影、夜間監視器及行車紀錄器等應用中，拍攝環境是屬於較陰暗或亮度不均勻的情況，由於一般顯示裝置的亮度呈現範圍狹小，導致輸出影像難以完整呈現所有細節。因此，一個適用於陰暗或不均勻亮度拍攝環境的影像強化技術是相當重要且吸引人的議題。此外，影像強化技術常常被實作在需要即時運算的電子產品當中，所以一個效果良好、低複雜度且適合以VLSI硬體電路實現的影像強化技術更是不可或缺的。
在本論文中，我們發展一個基於經驗模態分解(Empirical Mode Decomposition, EMD) 技術的影像強化演算法。我們採用快速適應二維經驗模態分解(Fast and Adaptive Bi-dimensional Empirical Mode Decomposition, FABEMD)方法的架構，並改良訊號的組合方式來有效地偵測影像中的高頻資訊。而為了改善gamma correction的缺點，所提出的方法使用一個adaptive pixel-based gamma correction，以保留更多的影像細節資訊。
針對所設計方法，我們也開發其相對應的VLSI電路架構並使用Verilog硬體描述語言實現該電路。根據Synopsys的Design Vision和TSMC 0.13μm的標準元件庫合成結果，該電路所需的邏輯閘數目為16K，工作時脈為5ns，平均功率消耗為19.8mW，並可達到200百萬像素/秒處理量，其處理速度滿足Full HD(1920*1080)每秒30張影像的格式需求。

In some image applications, such as endoscopy, night monitors, vehicle camera, the display devices can’t work well under darker environment or unequal light source because the illumination expressive range in general devices is narrow and small. Thus, the image enhancement method which is suitable for darker environment or unequal light source becomes a very important and attractive issue. Moreover, image enhancement technique usually implement in many electric products which require real-time processing. To achieve the goal of real time processing and low-cost VLSI implementation, an efficient and low complexity image enhancement method is needed.
For the above mentioned reason, we proposed an image enhancement algorithm based on empirical mode decomposition. To reduce the computing resource and improve the detail information of the shades, we adopt the fast and adaptive bidimensional empirical mode decomposition and modify its algorithm by using the fixed window. To improve the disadvantage of gamma correction, we propose an adaptive pixel-based gamma correction to solve the problem which loses detail information in light blocks. It can estimate intensity of lights with each pixel and keep more detail information adequately.
The VLSI architecture of our proposed design is implemented by using Verilog HDL. We used Synopsys Design Vision to synthesize the designs with TSMC 0.13μm cell library. Synthesis results show that the design circuit contains 16K gate counts and average power consumption requires 19.8mW. It works with a clock period of 5 ns and can achieve a processing rate of 200 mega pixels per second which is quick enough to process a video resolution of Full HD (1920×1024) at 30 fps in real time.

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