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研究生：	陳俊庭 Chen, Chun-Ting
論文名稱：	相異製程對鰭式場效電晶體特性與可靠度影響之研究 Effects of Different Processes on the Characteristics and Reliability of FinFET
指導教授：	陳志方 Chen, Jone-Fang
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	72
中文關鍵詞：	鰭式場效電晶體、熱載子退化、負偏壓溫度不穩定性、鰭式閘極寬度、鰭式閘極高度
外文關鍵詞：	FinFET, hot carrier effect, negative bias temperature instability, fin width, fin height
相關次數：	點閱：113 下載：0
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在本篇論文中，我們所使用的的元件為先進製程鰭式場效電晶體(Advanced-FinFETs)，其中將針對鰭式閘極不同寬度(fin width)與高度(fin height)的元件進行基本電性的量測、N型元件的熱載子可靠度與P型元件的負偏壓溫度不穩定性之探討。
首先，我們將說明此論文的研究動機並描述鰭式場效電晶體的結構、優缺點以及應用的領域，再來提及熱載子效應與負偏壓溫度不穩定性的基本原理。接著，介紹本論文中的量測手法及偏壓條件的設定以及說明可靠度評估的依據與其電壓的設置。
本篇的第一部分是研究不同鰭式閘極寬度(fin width)的元件對於元件特性及可靠度的影響，量測的結果顯示相異鰭式閘極寬度對於元件的基本電性沒有明顯的影響。在N型元件的熱載子可靠度方面，元件的退化主要受到介面陷阱電荷影響，而在P型元件的負偏壓溫度不穩定性當中，則是由氧化層缺陷主導退化。不同鰭式閘極寬度元件的電性退化趨勢沒有明顯差異，元件退化的物理機制與缺陷位置也不會受到鰭式閘極寬度的影響，我們推測是由於鰭式閘極寬度的差異太小，因此不會明顯地影響元件的電性與可靠度。
第二部分，我們分析不同鰭式閘極高度(fin height)的元件，量測結果顯示元件的基本電性沒有明顯的差異。在N型熱載子可靠度方面，元件的退化主要受到介面陷阱影響，而在P型負偏壓溫度不穩定性當中，則是由氧化層缺陷主導退化。不同鰭式閘極高度元件的電性退化趨勢並沒有明顯差異，退化的物理機制與缺陷位置也不會受到閘極高度的影響，我們推測是因為元件鰭式閘極高度的差異過於微小，因此不會對元件的電性與可靠度造成影響。

In this thesis, we analyzed on devices with different fin width and different fin height for basic electrical characteristics, N-type device hot carrier reliability (HCI) and p-type device negative bias temperature instability (NBTI) in advanced-FinFET. In our study, we used two devices with different fin width and fin height respectively.
Initially, we explained the motivation of this study and introduced the structure of FinFETs. The advantage, disadvantage, and application were also presented in this work. In addition, hot carrier effect and NBTI physical mechanism would be mentioned. Next, we introduced the measurement method and the setting of bias condition in this thesis, the measurement results for ID-VG and ID-VD of the basic electrical characteristics of the FinFETs would also be demonstrated.
In first part, we discussed the effect of fin width on advanced-FinFET. The measurement results showed that the different fin width has no significant effect on the basic electrical properties of the device. In the reliability of the N-type hot carrier, the degradation of the device is influenced by the interface trap. As for P-type negative bias temperature instability, the oxide layer defect dominates the degradation. There is no significant difference between the electrical degradation trend and magnitude of different fin width. The reason may be the differences between fin width are too small.
In the second part, the devices with different fin height were investigated. The results of the measurements also showed that there is no significant difference in the basic electrical properties of the devices. In the reliability of the N-type hot carrier injection, the degradation of the device is affected by the interface trap. As for the P-type negative bias temperature instability, the oxide layer defect dominates the degradation. However, the experiment results showed that it would not obviously affect the device and the physical mechanism and defect location would not be influenced by the fin height. Similarly, the reason may be the differences between fin height are too small. Therefore, it will not directly affect the electrical and reliability of the devices.

中文摘要	I
Abstract	III
致謝	V
Content	VI
Table Captions	VIII
Figure Captions	IX
Chapter1_Introduction	1
1-1 Motivation	1
1-2 Introduction of FinFET device and applications	3
1-3 Introduction of hot carrier reliability	3
1-4	Introduction of negative bias temperature instability reliability	5
1-5 About this thesis	7
Chapter 2_Device Characteristics and Measurement Setup	14
2-1 Introduction	14
2-2 Devices structure description	14
2-3 Measurement setup	15
2-3-1 Measurement setup	15
2-3-2 ID-VG measurement	16
2-3-3 ID-VD measurements	16
2-4 Stress condition	17
2-4-1 Stress measurement setup	17
2-4-2 NMOS hot carrier stress (HCI)	17
2-4-3 PMOS negative bias temperature instability stress (NBTI)	18
2-5 Summary	19
Chapter 3_Investigation of Different Fin Width	28
3-1 Introduction	28
3-2 Analysis of fresh device characteristic	29
3-3 Analysis of NMOS HCI reliability	29
3-4 Analysis of PMOS NBTI reliability	32
3-5 Difference between NMOS HCI and PMOS NBTI	34
3-6 Summary	34
Chapter 4_Investigation of Different Fin Height	48
4-1 Introduction	48
4-2 Analysis of fresh device characteristic	49
4-3 Analysis of NMOS HCI reliability	50
4-4 Analysis of PMOS NBTI reliability	52
4-5 Difference between NMOS HCI and PMOS NBTI	53
4-6 Summary	54
Chapter 5_Conclusion and Future Work	65
5-1 Conclusion	65
5-2 Future work	66
Reference	67

Table 2-1 Extraction condition of device electrical parameters	26
Table 2-2 Electrical parameters of devices	26
Table 2-3 N-type device hot carrier stress condition	27
Table 2-4 P-type device NBTI stress condition	27
Table 2-5 Electrical curve measurement setup table	27
Table 3-1 The correspondence table of different fin width.	47
Table 4-1 The correspondence table of different fin height.	64
Fig. 1-1 The cross section through fin of FinFET device	8
Fig. 1-2 Previous research of drain current with different fin width [4].	8
Fig. 1-3 Previous research of drain current with different fin height [4]	8
Fig. 1-4 Previous research of different trends of HCI reliability with different fin width. [10].	9
Fig. 1-5 Previous research of different trends of HCI reliability with different fin width. [5].	9
Fig. 1-6 Previous research of NBTI reliability with different fin width[11].	10
Fig. 1-7 Previous research of different trends of HCI reliability with different fin height [12].	10
Fig. 1-8 FinFET devices applications.	11
Fig. 1-9 Illustration of hot carrier injection induced by impact ionization.	12
Fig. 1-10 Illustration of trap charges induced by hot carrier injection.	12
Fig. 1-11 Illustration of NBTI condition [21].	13
Fig. 1-12 Illustration of the physical mechanism of NBTI [21].	13
Fig. 2-1 TEM images of fin cross-sections [25].	20
Fig. 2-2 Illustration of advanced FinFET structure and material	20
Fig. 2-3 Agilent B1500A semiconductor device parameter analyzer	21
Fig. 2-4 Picture of the entire measuring machine	22
Fig. 2-5 ID-VG electrical curve in linear region of standard device.	22
Fig. 2-6 ID-VG electrical curve in saturation region of standard device.	23
Fig. 2-7 ID-VD electrical curve of	23
Fig. 2-8 The procedure of stress measurement.	24
Fig. 2-9 The impact ionization generation rate between NMOS and PMOS.[26]	25
Fig. 2-10 The degradation of BTI stress between NMOS and PMOS.[10]	25
Fig. 3-1 Illustration of FinFET schematic and top SEM view [6].	35
Fig. 3-2 Schematic illustration of layout and cross-section of a fin [28].	35
Fig. 3-3 Ids vs. Vgs characteristics of device with different fin width.	36
Fig. 3-4 Ioff vs. Idsat characteristics of device with different fin width.	36
Fig. 3-5 Ids vs. Vgs characteristics of N_largeCD under HCI stress.	37
Fig. 3-6 Idsat degradation vs. stress time of NMOSFETs under HCI stress for device N_largeCD and N_smallCD	37
Fig. 3-7 Vtlin shift vs. stress time of NMOSFETs under HCI stress for device N_largeCD and N_smallCD	38
Fig. 3-8 Lifetime vs. 1/Vds of NMOSFETs under HCI stress for device N_largeCD and N_smallCD	38
Fig. 3-9 Vth drift correlation to ID drift in the past research with different voltage stress [29].	39
Fig. 3-10 Idsat degradation vs. Vtlin shift of NMOSFETs under HCI stress for device N_largeCD and N_smallCD.	39
Fig. 3-11 Vt shift correlation to subthreshold swing degradation in the past research [30].	40
Fig. 3-12 Vt shift correlation to subthreshold swing degradation in device N_largeCD and N_smallCD.	40
Fig. 3-13 Subthreshold swing degradation vs. stress time of NMOSFETs under HCI stress for device N_largeCD and N_smallCD.	41
Fig. 3-14 The power law of Vtlin shift vs. stress time curve in the past research [31].	41
Fig. 3-15 The threshold voltage power law factor of NMOSFETs under HCI stress for device N_largeCD and N_smallCD.	42
Fig. 3-16 Ids vs. Vgs characteristics of device P_largeCD under NBTI stress.	42
Fig. 3-17 Idsat degradation vs. stress time of PMOSFETs under NBTI stress for device P_largeCD and P_smallCD.	43
Fig. 3-18 Vtlin shift vs. stress time of PMOSFETs under NBTI stress for device P_largeCD and P_smallCD.	43
Fig. 3-19 Lifetime vs. Vgs of PMOSFETs under NBTI stress for device P_largeCD and P_smallCD.	44
Fig. 3-20 Idsat degradation vs. Vtlin shift of PMOSFETs under NBTI stress for device P_largeCD and P_smallCD.	44
Fig. 3-21 Vt shift correlation to subthreshold swing degradation in device P_largeCD and P_smallCD	45
Fig. 3-22 Subthreshold swing degradation vs. stress time of NMOSFETs under HCI stress for device P_largeCD and P_smallCD.	45
Fig. 3-23 The power law of Vtlin shift vs. stress time curve in device P_largeCD and P_smallCD.	46
Fig. 3-24 The Vt shift vs. S.S. Degradation in PMOS and NMOS device.	46
Fig. 4-1 Illustration of fin height process.	55
Fig. 4-2 Cross-sectional TEM view in the past research [21].	55
Fig. 4-3 Ids vs. Vgs characteristics of device with different fin height.	56
Fig. 4-4 Ioff vs. Idsat characteristics of device with different	56
Fig. 4-5 Ids vs. Vgs characteristics while device N_largeH under HCI stress.	57
Fig. 4-6 Idsat degradation vs. stress time of NMOSFETs under HCI stress for device N_largeH and N_smallH.	57
Fig. 4-7 Vtlin shift vs. stress time of NMOSFETs under HCI stress for device N_largeH and N_smallH.	58
Fig. 4-8 Lifetime vs. 1/Vds of NMOSFETs under HCI stress for device N_largeH and N_smallH.	58
Fig. 4-9 Idsat degradation vs. Vtlin shift of NMOSFETs under HCI stress for device N_largeH and N_smallH.	59
Fig. 4-10 Vt shift vs. subthreshold swing degradation in device N_largeH and N_smallH.	59
Fig. 4-11 The threshold voltage power law factor of NMOSFETs under HCI stress for device N_largeH and N_smallH.	60
Fig. 4-12 Ids vs. Vgs characteristics of device P_largeH under NBTI stress.	60
Fig. 4-13 Idsat degradation vs. stress time of PMOSFETs under NBTI stress for device P_largeH and P_smallH.	61
Fig. 4-14 Vtlin shift vs. stress time of PMOSFETs under NBTI stress for device P_largeH and P_smallH.	61
Fig. 4-15 Lifetime vs. Vgs of PMOSFETs under NBTI stress for device P_largeH and P_smallH.	62
Fig. 4-16 Idsat degradation vs. Vtlin shift of PMOSFETs under NBTI stress for device P_largeH and P_smallH.	62
Fig. 4-17 Vt shift correlation to subthreshold swing degradation in device P_largeH and P_smallH.	63
Fig. 4-18 The power law of Vtlin shift vs. stress time curve in device P_largeH and P_smallH.	63
Fig. 4-19 The Vt shift vs. S.S. Degradation in PMOS and NMOS device.	64



                                    

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校內：2024-06-27公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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