半導體元件製程的演進上，傳統的去耦合電漿氮化與氮化後退火處理在平面後金屬閘極金屬氧化物半導體元件的製造上，可以鞏固氧原子避免擴散至高介電係數介面層氧化物，降低元件的平帶電壓急遽下降，但是在三維立體結構金屬氧化物半導體元件製作上，會遇到瓶頸，因此在本論文中，藉由調變原子層級沉積溫度變化，並在氮化鈦金屬沉積後製程加上退火與額外的高溫氨氣侵入，提供了高介電係數介面層氧化物處理的新途徑。降低子層級沉積溫度可以減少柵極漏電流密度（Jg），改善平帶電壓（Vfb）和有效功函數（EWF），但是此法會等效氧化層的厚度。然而，透過添加額外的後金屬沉積退火和額外的高溫氨氣侵入製程，可以避免上述缺點。但是從柵極電介質開發的經驗來看，較高的氮化物濃度和氧化物厚度可能導致元件產生更多的界面陷阱和缺陷路徑。實驗結果顯示等效氧化層的厚度 (EOT) 的提昇會導致整體的閘極控制能力變弱。從反向思考，這也提供了一種降低金屬柵極厚度的方法，並可維持元件的特性。因此本研究成果可以為下一代三維立體結構金屬氧化物半導體元件微縮的製程開發上提供一個可能的解決方案。

To prevent the flat band voltage roll off of the 3-D MOSFET device, improve gate leakage and device performance, the experiment of ALD TiN temperature change, and add extra post metal deposition anneal with NH3 soak were introduced in this thesis. For the development of the IL / high-K gate last MOSFET or 3-D devices, this applicaiton provides a new path of the interfacial layer SiO2 and high-K Hf-silicate gate oxide treatment. To lower ALD deposition temperature can benefit fewer gate leakage current density (Jg) and improve the flat-band voltage (Vfb) and effective work function (EWF). The worse is to sacrifice the equivalent oxide thickness. By add extra post metal deposition anneal and NH3 soak process can improve the Jg, Vfb and EWF, but it will much more worse the EOT than the others condition. The higher nitride concentration and oxide thickness could caused device more interfacial traps and defect path from the experience of gate dielectric development. However, the thickness EOT also provide a way to thin down metal gate thickness and provide a potential method for the next generation 3-D MOSFET device development. From the tranditonal direct IL or high-K layer direct treatment to barrier layer soak process , this experiment provide a possible approach to the metal and oxide layers thickness thin down.

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