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研究生: 林晉則
Lin, Chin-Tse
論文名稱: 機器人的電腦圖學渲染及其FPGA實現
Computer Graphics Rendering of a Robot and Its FPGA Implementation
指導教授: 陳進興
Chen, Chin-Hsing
張名先
Chang, Ming-Xian
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2025
畢業學年度: 114
語文別: 英文
論文頁數: 77
中文關鍵詞: 現場可規劃邏輯電路即時3D繪圖機器人顯示管線化架構
外文關鍵詞: Field-Programmable Gate Array (FPGA), Real-Time 3D Rendering, Robot Display, Pipelined Architecture
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  • 本研究提出並實現一個基於FPGA的即時3D機器人顯示系統,以硬體化的方式實作3D繪圖流程,包含模型轉換(Model Transformation)、視角轉換 (View Transformation)、投影轉換(Projection Transformation)、遮擋判斷(Occlusion Handling) 與著色(Shading)。本系統使用Cyclone IV FPGA為開發平台,並輸出640×480 @ 60 Hz VGA訊號,以達成即時顯示需求。
    在設計方法上,系統採用多階段管線化與運算資源共享,並利用線性近似法實現三角函數運算,有效降低邏輯資源消耗,同時滿足即時運算之時序要求。為提升互動性,本研究開發一個Python圖形化介面(GUI),使用者可透過RS-232串列介面控制機器人模型之各個部位的旋轉角度,並立即在VGA畫面上呈現對應動作。
    實驗結果顯示,本系統能在有限的FPGA硬體資源下完成即時3D機器人圖形的顯示與控制,其中邏輯元素使用率約68%,記憶體使用率達80%。此結果驗證了設計架構在高資源壓力下仍能維持正確性與即時性。此成果不僅展示了 FPGA 在硬體圖形加速上的潛力,也可作為未來即時 3D 圖形處理與嵌入式視覺應用之參考基礎。

    This study proposes and implements an FPGA-based real-time 3D robot display system, in which the 3D graphics pipeline is realized in hardware. The implemented pipeline includes Model Transformation, View Transformation, Projection Transformation, Occlusion Handling, and Shading. The system is built on a Cyclone IV FPGA and outputs 640×480 @ 60 Hz VGA signals to achieve real-time display.
    In terms of design methodology, the system adopts a multi-stage pipelined architecture and resource sharing, while trigonometric functions are implemented using a piecewise linear approximation. This approach effectively reduces logic element usage while still meeting timing requirements for real-time computation. To enhance interactivity, a Python-based graphical user interface (GUI) was developed. Through the RS-232 serial interface, users can control the rotation angles of different robot body parts, and the corresponding movements are immediately displayed on the VGA screen.
    Experimental results show that the proposed system achieves real-time 3D robot rendering and control under limited FPGA hardware resources, with approximately 68% of logic elements and 80% of memory bits utilized. These results verify that the proposed architecture maintains correctness and real-time performance under high resource utilization. The outcome demonstrates the potential of FPGAs in hardware-accelerated graphics processing and can serve as a reference for future research on real-time 3D graphics and embedded visualization applications.

    摘 要 I Abstract III 誌 謝 V Acknowledgment VI Contents VIII List of Figures X Chapter 1 Introduction 1 1.1 Computer Graphics 1 1.2 Field Programmable Gate Array (FPGA) 2 1.3 Coordinate Transformation Pipeline for 3D Rendering 4 1.4 Motivation and Contribution 5 1.5 Thesis Organization 6 Chapter 2 Fundamentals and Related Work 7 2.1 Rasterization 7 2.2 Coordinate Transformation 8 2.2.1 Homogeneous Coordinates 8 2.2.2 Model Matrix 8 2.2.3 View Matrix 10 2.2.4 Projection Matrix 12 2.2.5 Perspective Division 15 2.2.6 Viewport Transformation 15 2.3 Barycentric Interpolation 17 2.4 Z-buffer Algorithm 18 2.5 Lighting Calculation 19 Chapter 3 Proposed Work 21 3.1 Equipment and Workflow 21 3.2 Graphical User Interface 22 3.3 The Top-Level Module 23 3.4 Control Unit Module 26 3.5 RS232 Receiver Module 27 3.6 Command Module 28 3.7 Movement Module 29 3.8 Project Module 35 3.9 Draw Module 38 3.10 Frame Buffer Module 43 3.11 VGA Controller Module 44 Chapter 4 Experimental Results 46 4.1 Research Equipment and Environment 46 4.2 Timing Violation and Pipeline Requirement 48 4.3 Final Rendering Results 50 Chapter 5 Discussion and Conclusion 58 5.1 Design Challenges and Solutions 58 5.2 Future Work 61 5.3 Conclusion 62 References 63

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