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研究生： 許博竣
Hsu, Po-Chun
論文名稱： 以CNN辨識數字的一心脈陣列FPGA實現
A FPGA Systolic Array Implementation of CNN for Recognition of Digits
指導教授： 陳進興
Chen, Chin-Hsing
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 53
中文關鍵詞： 現場可規劃邏輯電路 、心脈陣列 、卷積神經網路 、RS232
外文關鍵詞： filed programmable logic gate array (FPGA), systolic array, convolutional neural network (CNN), RS232
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    • 隨著人工智慧的普及和深度學習的複雜化，對硬體的運算能力的需求也越來越高。為了應對這一需求，高效能運算晶片變得至關重要。為此，本論文以心動陣列(SystolicArray)技術於現場可規劃邏輯電路(FPGA)實現一數字辨識系統。
    本論文採用卷積神經網路(CNN)架構來實現數字辨識，本論文的CNN架構包含兩層convolution layers、兩層max-pooling layers以及兩層full connection layers，其中convolution layers的卷積運算具有規律性，其卷積運算使用systolic array技術，來達到高效能運算。至於輸入的部分則是在PC端將影像處理成30 * 30的解析度並將RGB影像灰階化，再利用RS232模塊接收由PC傳輸的多筆數據做數字辨識，最終再利用RS232模塊將CNN辨識結果傳回到PC端顯示於螢幕上。
    使用心脈陣列與使用順序矩陣相乘之CNN架構相比較，前者具有處理速度快的優點，其辨識速度較使用順序矩陣相乘之CNN架構快了6倍，驗證了前者為一高效能數字辨識系統。

    Today, the application of artificial intelligence (AI) is pervades life, such as license plate recognition, face recognition, conversational robots, self-driving cars, etc. However, with the outbreak of the wave of AI, the deep learning model is becoming more and more complex and requires a huge calculation process. Therefore, high-performance computing Application Specific Integrated Circuit (ASIC) chips have become important. In this thesis, the systolic array technology is used to implement a digit recognition system on a field programmable gate array (FPGA), which can improve the system’s performance.
    This thesis utilizes a Convolutional Neural Network (CNN) architecture to implement a digit recognition system. The CNN architecture used in our system consists of two convolution layers, two max-pooling layers, and two fully connected layers. The convolution operation in the convolution layers is regular, therefore, systolic array technology is utilized in the convolutional layers to achieve high-performance computing. On the input side, the images are processed on the PC to a resolution of 30 * 30 and converted to grayscale. The RS232 module is used to receive multiple data inputs transmitted from the PC for digit recognition. Finally, the CNN recognition data is transmitted back to the PC using the RS232 module to display the digit recognition result.
    Compared to CNN architectures with sequential matrix multiplication, our system offers the advantage of fast processing speed. The recognition speed of our systolic-based system is six times faster than the CNN architecture that uses sequential matrix multiplication which shows our system is a high-performance computational digit recognition system.

    摘 要 I Abstract III 誌　謝 V Acknowledgment VI Contents VII List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 Digit recognition method 1 1.2 Convolutional Neural Network (CNN) & Systolic array 1 1.3 Field Programmable Gate Array (FPGA) 2 1.4 Convolutional Neural Network (CNN) 3 1.5 Motivation and Contribution 3 1.6 Thesis Organization 4 Chapter 2 Background Knowledge related to the Proposed System 5 2.1 Deep Learning 5 2.2 Overview of CNN 6 2.2.1 Convolution Layers 6 2.2.2 Pooling Layers 6 2.2.3 Fully Connected Layers 6 2.2.4 Activation Function 7 2.2.5 Backpropagation in CNN 8 2.3 RGB to Grayscale 10 2.4 Systolic Array 11 2.5 Weight Stationary systolic array 12 2.6 Processing Element (PE) 17 Chapter 3 Hardware Implementation of the Proposed System 19 3.1 Implementation of the Proposed Algorithm 19 3.2 Overview of the Proposed System 20 3.2.1 The Cyclone IV E FPGA 22 3.2.2 Programming Interface 22 3.2.3 RS232 Interface 22 3.3 The top Module 23 3.4 RS232 Module 24 3.4.1 RS232 Receiver Module 24 3.4.2 Control_in Module 24 3.4.3 RS232 Receiver Module 25 3.5 Grayscale Threshold Module 26 3.6 CNN Module 26 3.7 CNN Transmitter Module 28 3.8 CNN Receiver Module 29 3.9 Systolic Array & PE Module 30 3.9.1 Systolic Array Module 30 3.9.2 PE Module 31 3.10 FC_Op Module 31 Chapter 4 Experimental Results 32 4.1 Research equipment and environment 32 4.2 Systolic Array for Matrix Multiplication 34 4.2.1 Matrix Multiplication 34 4.2.2 Systolic Array convolution operation 34 4.2.3 Comparing recognition performance 45 4.3 Digit Recognition 46 4.4 The resources of FPGA used by the Proposed System 48 Chapter 5 Conclusion and Future Work 49 References 51

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