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研究生: 李東穎
Li, Dong-Ying
論文名稱: 基於嵌入式系統設計與實現 SSD 研究平台
Design and Implementation of an Embedded System-Based SSD Research Platform
指導教授: 侯廷偉
Hou, Ting-Wei
學位類別: 碩士
Master
系所名稱: 工學院 - 工程科學系碩士在職專班
Department of Engineering Science (on the job class)
論文出版年: 2024
畢業學年度: 112
語文別: 中文
論文頁數: 70
中文關鍵詞: SSD PlatformWear Leveling演算法NAND 型快閃記憶體
外文關鍵詞: SSD Platform, Wear Leveling algorithm, NAND Flash
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  • NAND型快閃記憶體(Flash Memory)因成本低、尺寸小等優勢,廣泛應用於儲存裝置中。由於NAND型快閃記憶體在先天製程技術上有著擦除(Erase)次數的限制,會有很大的機率造成區塊(Block)毀損。市售 SSD (Solid State Drive)基本上都會有一個主控晶片來控制SSD中每一個區塊被擦除的次數,再經由耗損平均技術(Wear Leveling)將資料優先寫入擦除次數較少的區塊,減少特定區塊過度擦除,讓每一區塊能夠均勻地使用,從而延長SSD使用的壽命。
    在開發SSD相關應用演算法時除了模擬軟體外也需要硬體環境的支持,來比擬真實環境,例如OpenSSD是一個專為研究SSD,提供近似於真實環境的硬體平台,使用者可以在OpenSSD硬體上面依照其提供的通訊格式搭配適當的SSD等硬體環境,達到擬真硬體平台。本研究目標為建立高性價比與可擴充性的 SSD 硬體模擬平台,並在此平台上測試自行開發的Wear Leveling演算法來驗證平台的可行性。研究內容分兩大部分,分別為硬體平台建立與軟體驗證,第一部分以嵌入式平台為硬體基礎,將內建的Nand Flash 128 MB 更換成 256 MB並外接兩組256 MB Nand Flash以模擬SSD寫入與擦除的真實狀態,第二部分將實做Wear Leveling演算法來驗證第一部分平台的可行性。

    NAND flash memory is widely used in storage devices due to its low cost and small size, such as in common SD memory cards. However, it has limitations in program and erase cycles, leading to potential block failures. Commercial SSDs (Solid State Drives) typically use chips to control the erase cycles of each block. Wear Leveling technology prioritizes writing data to blocks with fewer erase cycles, ensuring even usage and extending SSD lifespan.
    When developing algorithms for SSD applications, both simulation software and hardware environments are necessary to mimic real-world conditions. OpenSSD, for instance, provides a hardware platform for SSD research, allowing users to emulate real environments by configuring SSD hardware based on its communication format. This study aims to establish a cost-effective and scalable SSD hardware simulation platform. It involves two main components: hardware platform setup and software verification. The first part utilizes the embedded platform, replacing the built-in 128 MB NAND Flash with 256 MB and connecting two additional 256 MB NAND Flash modules to simulate real SSD write and erase scenarios. The second part implements Wear Leveling algorithms to validate the feasibility of the hardware platform established in the first part.

    摘要 I Extended Abstract II 致謝 VII 目錄 VIII 表目錄 IX 圖目錄 X 第一章 緒論 1 1.1 研究動機與目的 1 1.2 文獻回顧 2 1.3 研究方法與論文架構 5 第二章 研究內容相關介紹 8 2.1 Flash介紹 8 2.2 SSD介紹 11 2.3 SSD上常見的損壞名詞介紹 11 2.4 Blocks Management 13 2.5 Memory Technology Devices 16 2.6 NuMaker-IIoT-NUC980硬體架構與規格 16 第三章 研究方法 18 3.1 研究流程 18 3.2 系統架構 21 3.3 硬體實作方法與流程 21 3.4 軟體實作流程與使用方式 24 3.4 實作Wear Leveling演算法 34 第四章 實作結果與討論 36 4.1 實驗環境與方法 36 4.2 軟硬體測試方式 38 4.3 OpenSSD與NuMaker-IIoT-NUC980硬體架構比較 40 4.4 實驗結果 42 4.5 實驗討論 45 第五章 結論與未來展望 46 5.1 結論 46 5.2 未來展望 47 參考文獻 48 附錄一 Linux Driver 新增/修改部分 51

    [1] OpenSSD, http://www.openssd-project.org/.[Accessed 15 Oct., 2023]
    [2] Y. Luyang , L. Yizhen, M. Meghna, R. Edward, M.Vikram Sharma, M. Seung Won, H. Wen-mei, C. Deming, “FSSD: FPGA-based Emulator for SSDs”, 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), USA, pp. 101-108.
    [3] QEMU,https://www.qemu.org/.[Accessed 15 Oct., 2023]
    [4] FEMU,https://github.com/vtess/FEMU. [Accessed 15 Oct., 2023]
    [5] M. Jung, J. Zhang, A. Abulila, M. Kwon, N. Shahidi, J. Shalf, Nam Sung Kim, and M. Kandemir, “SimpleSSD: Modeling Solid State Drives for Holistic System Simulation”, IEEE Computer Architecture Letters, vol. 17, no. 1, Korea, 2018, pp. 37-41.
    [6] C. Park, D. Lee, and S. Cho, “Write Endurance in Flash SSD: Measurements and Analysis”, 2015 IEEE 34th Symposium on Mass Storage Systems and Technologies (MSST), Korea, 2018, pp. 1-6.
    [7] H. Zhou, F. Wu, and X. Qin, “Write Amplification Analysis in Flash-based Solid State Drives”, 2014 IEEE 22nd International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Switzerland, 2014 , pp. 186-195.
    [8] K. H. Tsoi, P. P. C. Lee, and J. S. Plank, “Temperature Dependence of Flash Memory Retention”, 2006 43rd ACM/IEEE Design Automation Conference, USA, 2006, pp. 680-685.
    [9] A. Schmid, S. Bux, and N. Wehn, “Impact of Flash Memory Density and Temperature on Error Rates”, 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Germany, 2011, pp. 88-94.
    [10] A. M. Alameldeen, M. A. Kozuch, K. E. Moore, and T. F. Wenisch, “Understanding the Impact of Emerging Non-volatile Memories on High-performance, IO-bound Computing”, 2013 IEEE 19th International Symposium on High Performance Computer Architecture, New Orleans, LA, USA, 2013, pp. 1-12.
    [11] R. Iyer, P. Shirley, and T. R. Halfhill, “An Efficient Wear Leveling Algorithm for Large Scale Flash Memory Storage Systems”, ACM SIGMETRICS Performance Evaluation Review, vol. 37, no. 1, pp. 59-66.
    [12] C. Park, D. Lee, and S. Cho, “Garbage Collection Policy for Flash-Based SSDs“, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), Korea, 2015, pp. 468-479.
    [13] 維基百科,“非揮發性記憶體”,23 Dec., 2022,https://reurl.cc/A0LbNQ. [Accessed 15 Oct., 2023]
    [14] Kingston Technology Co., Ltd., “什麼是NAND”,Apr. 2021,https://reurl.cc/a48M29. [Accessed 15 Oct., 2023]
    [15] 凌威科技,“SSD 固態硬碟原理,帶你進一步分析”,Aug. 14 2021,https://www.linwei.com.tw/forum-detail/23/.[Accessed 15 Oct., 2023]
    [16] ADATA Co., Ltd., “壞塊管理 (Bad Block Management) ”,https://reurl.cc/RyE9ar. [Accessed 15 Oct., 2023]
    [17] L. Xin, N. Yuehua, Y. Jiyang, Z. Yi, “A Bad Block Management Design Based on SpaceBorne Nand Flash Parallel Storage System”, 2022 14th International Conference on Communication Software and Networks, Aug. 22, 2022, pp. 114-118.
    [18] Z. Yanbin, Y. Qi, “A Multiple Bits Error Correction Method Based on Cyclic Redundancy Check Codes”, 2008 9th International Conference on Signal Processing, Apr. 08, 2008, pp.1808-1810.
    [19] W. Guohui, H. Yongjie, W. Jian, “NAND Flash Bad Block Management Research Based On FPGA”, 2015 International Conference on Applied Science and Engineering Innovation, 2015. Pp.149-152.
    [20] H. Yonghao, W. Shaoyun, “Design and implementation of a Flash NAND dynamic bad block Management algorithm”, Information research, 2014, pp. 23-26.
    [21] ADATA Co., Ltd., “耗損平均 (Wear Leveling) ”,https://reurl.cc/z64Q8V. [Accessed 15 Oct., 2023]
    [22] Memory Technology Devices, “General MTD documentation”,https://pse.is/5jur29. [Accessed 15 Oct., 2023]
    [23] G. Thomas, “MTD NAND Driver Programming Interface”,https://pse.is/5juq4n. [Accessed 15 Oct., 2023]
    [24] Nuvoton Technology Co., Ltd.,, “NuMaker-IIoT-NUC980”,https://pse.is/5juq3v. [Accessed 15 Oct., 2023]
    [25] Winbond Co., Ltd.,“3V 2G-Bit SLC QSPINAND Flash Memory with Dual/Quad SPI Buffer Read & Sequential Read”, Mar. 21, 2023.
    [26] Nuvoton Technology Co., Ltd., “NuMaker-Server-NUC980”,https://reurl.cc/7MLEel. [Accessed 15 Oct., 2023]
    [27] M. Murugan , D. H. C. Du, “Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead”, Proc. IEEE 27th Symp. Mass Storage Syst. Technol (MSST), May., 2011, pp. 1-12.

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