| 研究生: |
李東穎 Li, Dong-Ying |
|---|---|
| 論文名稱: |
基於嵌入式系統設計與實現 SSD 研究平台 Design and Implementation of an Embedded System-Based SSD Research Platform |
| 指導教授: |
侯廷偉
Hou, Ting-Wei |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 工程科學系碩士在職專班 Department of Engineering Science (on the job class) |
| 論文出版年: | 2024 |
| 畢業學年度: | 112 |
| 語文別: | 中文 |
| 論文頁數: | 70 |
| 中文關鍵詞: | SSD Platform 、Wear Leveling演算法 、NAND 型快閃記憶體 |
| 外文關鍵詞: | SSD Platform, Wear Leveling algorithm, NAND Flash |
| 相關次數: | 點閱:69 下載:0 |
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NAND型快閃記憶體(Flash Memory)因成本低、尺寸小等優勢,廣泛應用於儲存裝置中。由於NAND型快閃記憶體在先天製程技術上有著擦除(Erase)次數的限制,會有很大的機率造成區塊(Block)毀損。市售 SSD (Solid State Drive)基本上都會有一個主控晶片來控制SSD中每一個區塊被擦除的次數,再經由耗損平均技術(Wear Leveling)將資料優先寫入擦除次數較少的區塊,減少特定區塊過度擦除,讓每一區塊能夠均勻地使用,從而延長SSD使用的壽命。
在開發SSD相關應用演算法時除了模擬軟體外也需要硬體環境的支持,來比擬真實環境,例如OpenSSD是一個專為研究SSD,提供近似於真實環境的硬體平台,使用者可以在OpenSSD硬體上面依照其提供的通訊格式搭配適當的SSD等硬體環境,達到擬真硬體平台。本研究目標為建立高性價比與可擴充性的 SSD 硬體模擬平台,並在此平台上測試自行開發的Wear Leveling演算法來驗證平台的可行性。研究內容分兩大部分,分別為硬體平台建立與軟體驗證,第一部分以嵌入式平台為硬體基礎,將內建的Nand Flash 128 MB 更換成 256 MB並外接兩組256 MB Nand Flash以模擬SSD寫入與擦除的真實狀態,第二部分將實做Wear Leveling演算法來驗證第一部分平台的可行性。
NAND flash memory is widely used in storage devices due to its low cost and small size, such as in common SD memory cards. However, it has limitations in program and erase cycles, leading to potential block failures. Commercial SSDs (Solid State Drives) typically use chips to control the erase cycles of each block. Wear Leveling technology prioritizes writing data to blocks with fewer erase cycles, ensuring even usage and extending SSD lifespan.
When developing algorithms for SSD applications, both simulation software and hardware environments are necessary to mimic real-world conditions. OpenSSD, for instance, provides a hardware platform for SSD research, allowing users to emulate real environments by configuring SSD hardware based on its communication format. This study aims to establish a cost-effective and scalable SSD hardware simulation platform. It involves two main components: hardware platform setup and software verification. The first part utilizes the embedded platform, replacing the built-in 128 MB NAND Flash with 256 MB and connecting two additional 256 MB NAND Flash modules to simulate real SSD write and erase scenarios. The second part implements Wear Leveling algorithms to validate the feasibility of the hardware platform established in the first part.
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校內:2029-01-26公開