本論文主要針對環繞型金氧半場效電晶體(GAAFET)做電晶體模型的探討且以TCAD模擬電晶體特性，由於電晶體尺寸較小，不能只使用傳統熱平衡飄移擴散模型(Drift-Diffusion model)，需要使用Landauer方法來計算彈道模型(Ballistic model)，並且推導次臨界電流，實現以model預測電晶體與反向器(inverter)電路行為的目標，並且希望能夠往更多電路(如SRAM)等的電路做推導。
元件的低溫特性也相當重要，可觀察到次臨界擺幅(Subthreshold Swing)隨著溫度降低後飽和的現象與導通電流(Ion)隨著溫度降低升高又下降的趨勢，並且希望這些元件行為能夠往電路的低溫特性做研究。
將GAAFET上下堆疊組成互補式場效電晶體(CFET)，可大幅減小電路面積，降低成本與功耗並增加電路效率，成為下一代半導體製程技術的研究方向，本文以CFET為發想，製作以上下堆疊的靜態隨機存取記憶體(SRAM)，提出了最佳的cell ratio與pull-up ratio 之比例，並比較其功耗。

This thesis focuses on the modeling of Gate-All-Around Field-Effect Transistors (GAAFETs) and the simulation of their characteristics using TCAD. Due to the small dimensions of the devices, the conventional thermodynamic drift-diffusion model is insufficient. Instead, the Landauer approach is employed to construct a ballistic model, which assumes carrier transport without scattering in short-channel devices. The subthreshold current is derived based on this model to enable prediction of both device and inverter circuit behavior, with the aim of extending the modeling framework to more complex circuits such as SRAM.
Low-temperature behavior of the devices is also crucial. Notably, the subthreshold swing (SS) tends to saturate as temperature decreases, and the on-state current (Ion) initially increases and then decreases at lower temperatures. These observations motivate further exploration of circuit-level characteristics under cryogenic conditions.
By vertically stacking GAAFETs, a complementary field-effect transistor (CFET) architecture is constructed, significantly reducing circuit area, cost, and power consumption while improving performance. This approach aligns with the development direction of next-generation semiconductor technologies. Inspired by CFET, this work designs a vertically stacked static random-access memory (SRAM) cell, proposes optimal cell ratio and pull-up ratio configurations, and compares their corresponding power consumption.

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