本研究針對堆疊式多通道全閘極環繞結構之氧化鋅銦鎵電晶體進行製程開發與系統性優化，旨在提升元件電性表現與操作穩定性。透過設計一至三層不同通道堆疊結構，探討其對導通電流、閘極調控能力與次臨界擺幅等關鍵參數之影響，並比較新舊製程條件，改善通道釋放與閘極堆疊完整性，使元件達成優異的開關特性與閘極控制能力。為抑制氧空缺引發之載子濃度不均與不穩定性，本研究引入氟摻雜機制，並結合臭氧介面與快速熱氧化處理，有效促進薄膜內部重組與缺陷鈍化。藉由X光光電子能譜、差分霍爾量測與原子力顯微鏡等材料分析工具，驗證各製程對鍵結狀態、表面形貌與載子濃度之影響，並進一步與電性結果建立對應關係。電性量測顯示，單層與雙層結構已具備穩定開關行為與良好驅動能力，三層通道元件則展現提升整合密度與性能極限之潛力。本研究成功建立一套適用於低溫製程條件下之堆疊式全閘極環繞電晶體開發平台，具備高度製程相容性與擴充潛力，為未來三維堆疊整合、低功耗透明電子元件與先進記憶體應用奠定技術基礎。

This study focuses on the process development and systematic optimization of stacked multi-channel gate-all-around transistors based on indium gallium zinc oxide (IGZO), aiming to enhance device electrical performance and operational stability. By designing one- to three-layer channel stack structures, the effects on key parameters such as on-state current, gate controllability, and subthreshold swing were investigated. A comparison between the conventional and modified process flows was carried out to improve the channel release and gate stack integrity, resulting in excellent switching behavior and gate control capability. To suppress carrier concentration inhomogeneity and instability induced by oxygen vacancies, a fluorine doping mechanism was introduced, combined with ozone-based interfacial treatment and rapid thermal oxidation, which effectively promoted film reorganization and defect passivation. Material characterization techniques including X-ray photoelectron spectroscopy, differential Hall measurements, and atomic force microscopy were employed to verify the effects of each process on bonding states, surface morphology, and carrier concentration, further correlating with electrical characteristics. Electrical measurements revealed that both single- and double-channel devices exhibited stable switching behavior and good driving capability, while the triple-channel structure demonstrated promising potential for enhanced integration density and performance limits. Overall, this work successfully establishes a versatile development platform for stacked GAA TFTs under low-temperature processing conditions, offering high process compatibility and scalability, and laying a solid technical foundation for future applications in 3D integrated circuits, low-power transparent electronics, and advanced memory devices.

[1] B. Bush, J. Mack, L. Hanks, T. Collector, Z. Cai, A. Naeemi, and D. E. Shim, "Exploring FinFET and Gate-All-Around FET for SRAM Cell Arrays at the 3 nm Process Node," in 2023 IEEE International Opportunity Research Scholars Symposium (ORSS), 23 April-2 June 2023 2023, pp. 43-46, doi: 10.1109/ORSS58323.2023.10161740.
[2] W. Hu and F. Li, "Scaling Beyond 7nm Node: An Overview of Gate-All-Around FETs," in 2021 9th International Symposium on Next Generation Electronics (ISNE), 9-11 July 2021 2021, pp. 1-6, doi: 10.1109/ISNE48910.2021.9493305.
[3] S. V. Kalinin, D. I. Ostertak, D. A. Poteryaev, and M. A. Kuznetsov, "A New Revolution in Logic Silicon IC Technology: GAA FETs are Replacing FinFETs," in 2023 IEEE XVI International Scientific and Technical Conference Actual Problems of Electronic Instrument Engineering (APEIE), 10-12 Nov. 2023 2023, pp. 160-165, doi: 10.1109/APEIE59731.2023.10347677.
[4] S. W. Chang, P. J. Sung, T. Y. Chu, D. D. Lu, C. J. Wang, N. C. Lin, C. J. Su, S. H. Lo, H. F. Huang, J. H. Li, M. K. Huang, Y. C. Huang, S. T. Huang, H. C. Wang, Y. J. Huang, J. Y. Wang, L. W. Yu, Y. F. Huang, F. K. Hsueh, C. T. Wu, W. C. Y. Ma, K. H. Kao, Y. J. Lee, C. L. Lin, R. W. Chuang, K. P. Huang, S. Samukawa, Y. Li, W. H. Lee, T. S. Chao, G. W. Huang, W. F. Wu, J. Y. Li, J. M. Shieh, W. K. Yeh, and Y. H. Wang, "First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications," in 2019 IEEE International Electron Devices Meeting (IEDM), 7-11 Dec. 2019 2019, pp. 11.7.1-11.7.4, doi: 10.1109/IEDM19573.2019.8993525.
[5] J. Ryckaert, P. Schuddinck, P. Weckx, G. Bouche, B. Vincent, J. Smith, Y. Sherazi, A. Mallik, H. Mertens, S. Demuynck, T. H. Bao, A. Veloso, N. Horiguchi, A. Mocuta, D. Mocuta, and J. Boemmels, "The Complementary FET (CFET) for CMOS scaling beyond N3," in 2018 IEEE Symposium on VLSI Technology, 18-22 June 2018 2018, pp. 141-142, doi: 10.1109/VLSIT.2018.8510618.
[6] S. Subramanian, M. Hosseini, T. Chiarella, S. Sarkar, P. Schuddinck, B. T. Chan, D. Radisic, G. Mannaert, A. Hikavyy, E. Rosseel, F. Sebaai, A. Peter, T. Hopf, P. Morin, S. Wang, K. Devriendt, D. Batuk, G. T. Martinez, A. Veloso, E. D. Litta, S. Baudot, Y. K. Siew, X. Zhou, B. Briggs, E. Capogreco, J. Hung, R. Koret, A. Spessot, J. Ryckaert, S. Demuynck, N. Horiguchi, and J. Boemmels, "First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers," in 2020 IEEE Symposium on VLSI Technology, 16-19 June 2020 2020, pp. 1-2, doi: 10.1109/VLSITechnology18217.2020.9265073.
[7] S. K. Moore. (2023) Meet the Forksheet: Imec’s In-Between Transistor The architecture shrinks circuits in a valuable step toward the ultimate CMOS device. IEEE Spectrum. Available: https://spectrum.ieee.org/forksheet-transistor
[8] S. Datta, S. Dutta, B. Grisafe, J. Smith, S. Srinivasa, and H. Ye, "Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration," IEEE Micro, vol. 39, no. 6, pp. 8-15, 2019, doi: 10.1109/MM.2019.2942978.
[9] J. L. Prasanna, M. R. Kumar, C. Priyanka, and C. Santhosh, "Evaluation of Device Fabrication from FET to CFET: A Review," Journal of Nano- and Electronic Physics, vol. 13, no. 6, pp. 06030-1-06030-8, 2021, doi: 10.21272/jnep.13(6).06030.
[10] R. An, Y. Li, J. Tang, B. Gao, Y. Du, J. Yao, Y. Li, W. Sun, H. Zhao, J. Li, Q. Qin, Q. Zhang, S. Qiu, Q. Li, Z. Li, H. Qian, and H. Wu, "A Hybrid Computing-In-Memory Architecture by Monolithic 3D Integration of BEOL CNT/IGZO-based CFET Logic and Analog RRAM," presented at the 2022 International Electron Devices Meeting (IEDM), 2022.
[11] Y. J. Jang, A. Sharma, and J. P. Jung, "Advanced 3D Through-Si-Via and Solder Bumping Technology: A Review," Materials (Basel), vol. 16, no. 24, Dec 14 2023, doi: 10.3390/ma16247652.
[12] J. Wang, F. Duan, Z. Lv, S. Chen, X. Yang, H. Chen, and J. Liu, "A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis," Applied Sciences, vol. 13, no. 14, 2023, doi: 10.3390/app13148301.
[13] K. Acharya, K. Chang, K. Bon Woong, S. Panth, S. Sinha, B. Cline, G. Yeric, and S. K. Lim, "Monolithic 3D IC design: Power, performance, and area impact at 7nm," in 2016 17th International Symposium on Quality Electronic Design (ISQED), 15-16 March 2016 2016, pp. 41-48, doi: 10.1109/ISQED.2016.7479174.
[14] Q. Li, C. Gu, S. Zhu, Q. Hu, W. Zhao, X. Li, R. Huang, and Y. Wu, "BEOL-Compatible High-Performance a-IGZO Transistors with Record high Ids,max = 1207 μA/μm and on-off ratio exceeding 1011 at Vds = 1V," in 2022 International Electron Devices Meeting (IEDM), 3-7 Dec. 2022 2022, pp. 2.7.1-2.7.4, doi: 10.1109/IEDM45625.2022.10019448.
[15] C. Niu, P. Tan, J.-Y. Lin, L. Long, Z. Lin, Y. Zhang, H. Wang, G. D. Wilk, and P. D. Ye, "First Demonstration of BEOL Wafer-Scale All-ALD Channel CFETs Using IGZO and Te for Monolithic 3D Integration," presented at the 2024 IEEE International Electron Devices Meeting (IEDM), 2024.
[16] S. Barraud, B. Previtali, C. Vizioz, J. M. Hartmann, J. Sturm, J. Lassarre, C. Perrot, P. Rodriguez, V. Loup, A. Magalhaes-Lucas, R. Kies, G. Romano, M. Cassé, N. Bernier, A. Jannaud, A. Grenier, and F. Andrieu, "7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing," in 2020 IEEE Symposium on VLSI Technology, 16-19 June 2020 2020, pp. 1-2, doi: 10.1109/VLSITechnology18217.2020.9265025.
[17] J. C. Chiu, E. Sarkar, Y. M. Liu, Y. C. Chen, Y. C. Fan, and C. W. Liu, "First Demonstration of a-IGZO GAA Nanosheet FETs Featuring Achievable SS=61mV/dec,Ioff <-7 μA/μm, DIBL =44mV/V, Positive VT, and Process Temp. of 300 °C," in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 11-16 June 2023 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185385.
[18] P. J. Sung, S. W. Chang, K. H. Kao, C. T. Wu, C. J. Su, T. C. Cho, F. K. Hsueh, W. H. Lee, Y. J. Lee, and T. S. Chao, "Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters," IEEE Transactions on Electron Devices, vol. 67, no. 9, pp. 3504-3509, 2020, doi: 10.1109/TED.2020.3007134.
[19] S. W. Chang, T. H. Lu, C. Y. Yang, C. J. Yeh, M. K. Huang, C. F. Meng, P. J. Chen, T. H. Chang, Y. S. Chang, J. W. Jhu, T. C. Hong, C. C. Ke, X. R. Yu, W. H. Lu, M. A. Baig, T. C. Cho, P. J. Sung, C. J. Su, F. K. Hsueh, B. Y. Chen, H. H. Hu, C. T. Wu, K. L. Lin, W. C. Y. Ma, D. D. Lu, K. H. Kao, Y. J. Lee, C. L. Lin, K. P. Huang, K. M. Chen, Y. Li, S. Samukawa, T. S. Chao, G. W. Huang, W. F. Wu, W. H. Lee, J. Y. Li, J. M. Shieh, J. H. Tarng, Y. H. Wang, and W. K. Yeh, "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, 2022, doi: 10.1109/TED.2021.3138947.
[20] Q. Shangguan, Y. Lv, and C. Jiang, "A Review of Wide Bandgap Semiconductors: Insights into SiC, IGZO, and Their Defect Characteristics," Nanomaterials (Basel), vol. 14, no. 20, Oct 19 2024, doi: 10.3390/nano14201679.
[21] J. Shi, J. Zhang, L. Yang, M. Qu, D. C. Qi, and K. H. L. Zhang, "Wide Bandgap Oxide Semiconductors: from Materials Physics to Optoelectronic Devices," Adv Mater, vol. 33, no. 50, p. e2006230, Dec 2021, doi: 10.1002/adma.202006230.
[22] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors," Nature, vol. 432, no. 7016, pp. 488-492, 2004/11/01 2004, doi: 10.1038/nature03090.
[23] H. Hosono, M. Yasukawa, and H. Kawazoe, "Novel oxide amorphous semiconductors: transparent conducting amorphous oxides," Journal of Non-Crystalline Solids, vol. 203, pp. 334-344, 1996/08/01/ 1996, doi: https://doi.org/10.1016/0022-3093(96)00367-5.
[24] H. Hosono, N. Kikuchi, N. Ueda, and H. Kawazoe, "Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples," Journal of Non-Crystalline Solids, vol. 198-200, pp. 165-169, 1996/05/02/ 1996, doi: https://doi.org/10.1016/0022-3093(96)80019-6.
[25] T. Kamiya, K. Nomura, and H. Hosono, "Present status of amorphous In–Ga–Zn–O thin-film transistors," Science and Technology of Advanced Materials, vol. 11, no. 4, p. 044305, 2010/02/01 2010, doi: 10.1088/1468-6996/11/4/044305.
[26] J. Sheng, T. Hong, H.-M. Lee, K. Kim, M. Sasase, J. Kim, H. Hosono, and J.-S. Park, "Amorphous IGZO TFT with High Mobility of ∼70 cm2/(V s) via Vertical Dimension Control Using PEALD," ACS Applied Materials & Interfaces, vol. 11, no. 43, pp. 40300-40309, 2019/10/30 2019, doi: 10.1021/acsami.9b14310.
[27] W. Assenmacher, G. Schnakenburg, Y. Michiue, Y. Kanke, N. Kimizuka, and W. Mader, "Synthesis and crystal structure characterization of InGaZnO4 with a new defect structure," Journal of Solid State Chemistry, vol. 215, pp. 176-183, 2014/07/01/ 2014, doi: https://doi.org/10.1016/j.jssc.2014.03.042.
[28] T. Kamiya, K. Nomura, and H. Hosono, "Origins of High Mobility and Low Operation Voltage of Amorphous Oxide TFTs: Electronic Structure, Electron Transport, Defects and Doping," Journal of Display Technology, vol. 5, no. 7, pp. 273-288, 2009, doi: 10.1109/JDT.2009.2021582.
[29] H. Peelaers, E. Kioupakis, and C. G. Van de Walle, "Limitations of In2O3 as a transparent conducting oxide," Applied Physics Letters, vol. 115, no. 8, p. 082105, 2019, doi: 10.1063/1.5109569.
[30] T. Kamiya, K. Nomura, and H. Hosono, "Subgap states, doping and defect formation energies in amorphous oxide semiconductor a-InGaZnO4 studied by density functional theory," physica status solidi (a), vol. 207, no. 7, pp. 1698-1703, 2010/07/01 2010, doi: https://doi.org/10.1002/pssa.200983772.
[31] K. Nomura, T. Kamiya, H. Ohta, T. Uruga, M. Hirano, and H. Hosono, "Local coordination structure and electronic structure of the large electron mobility amorphous oxide semiconductor In-Ga-Zn-O: Experiment and ab initio calculations," Physical Review B, vol. 75, no. 3, p. 035212, 01/18/ 2007, doi: 10.1103/PhysRevB.75.035212.
[32] A. de Jamblinne de Meux, A. Bhoolokam, G. Pourtois, J. Genoe, and P. Heremans, "Oxygen vacancies effects in a-IGZO: Formation mechanisms, hysteresis, and negative bias stress effects," physica status solidi (a), vol. 214, no. 6, p. 1600889, 2017/06/01 2017, doi: https://doi.org/10.1002/pssa.201600889.
[33] Y. Zhou, D. Wang, Y. Li, L. Jing, S. Li, X. Chen, B. Zhang, W. Shuai, R. Tao, X. Lu, and J. Liu, "Critical Effect of Oxygen Pressure in Pulsed Laser Deposition for Room Temperature and High Performance Amorphous In-Ga-Zn-O Thin Film Transistors," Nanomaterials, vol. 12, no. 24, doi: 10.3390/nano12244358.
[34] W. Zhang, Z. Fan, A. Shen, and C. Dong, "Atmosphere Effect in Post-Annealing Treatments for Amorphous InGaZnO Thin-Film Transistors with SiOx Passivation Layers," Micromachines, vol. 12, no. 12, doi: 10.3390/mi12121551.
[35] W. Körner, D. F. Urban, and C. Elsässer, "Origin of subgap states in amorphous In-Ga-Zn-O," Journal of Applied Physics, vol. 114, no. 16, p. 163704, 2013, doi: 10.1063/1.4826895.
[36] J. Bang, S. Matsuishi, and H. Hosono, "Hydrogen anion and subgap states in amorphous In–Ga–Zn–O thin films for TFT applications," Applied Physics Letters, vol. 110, no. 23, p. 232105, 2017, doi: 10.1063/1.4985627.
[37] H. Tang, K. Ishikawa, K. Ide, H. Hiramatsu, S. Ueda, N. Ohashi, H. Kumomi, H. Hosono, and T. Kamiya, "Effects of residual hydrogen in sputtering atmosphere on structures and properties of amorphous In-Ga-Zn-O thin films," Journal of Applied Physics, vol. 118, no. 20, p. 205703, 2015, doi: 10.1063/1.4936552.
[38] J.-s. Kim, B. S. Oh, M. Piao, M.-K. Joo, H.-K. Jang, S.-E. Ahn, and G.-T. Kim, "Effects of low-temperature (120 °C) annealing on the carrier concentration and trap density in amorphous indium gallium zinc oxide thin film transistors," Journal of Applied Physics, vol. 116, no. 24, p. 245302, 2014, doi: 10.1063/1.4904843.
[39] H. Kim, C. Han, D. Kim, and B. Choi, "Electrical Performance and Reliability Enhancement of a-IGZO TFTs via Post-N2O Plasma Optimization," IEEE Transactions on Electron Devices, vol. 70, no. 7, pp. 3611-3616, 2023, doi: 10.1109/TED.2023.3278620.
[40] J. Y. Lee, G. Tarsoly, F. Shan, and S. J. Kim, "Optimizing Oxygen Plasma Treatment Time to Improve the Characteristics of a-IGZO Thin-Film Transistors and Resistive-Load Inverters," IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1883-1888, 2022, doi: 10.1109/TED.2022.3144123.
[41] H. S. Shin, B. D. Ahn, Y. S. Rim, and H. J. Kim, "Annealing temperature dependence on the positive bias stability of IGZO thin-film transistors," Journal of Information Display, vol. 12, no. 4, pp. 209-212, 2011/12/01 2011, doi: 10.1080/15980316.2011.621331.
[42] S. H. Choi, M. H. Lim, W. S. Jung, and J. H. Park, "Impacts of the Thermal Recovery Process on In–Ga–Zn–O (IGZO) TFTs," IEEE Electron Device Letters, vol. 35, no. 8, pp. 835-837, 2014, doi: 10.1109/LED.2014.2329911.
[43] D. Choi, "Fluorine-doped indium gallium zinc oxide thin-film transistors fabricated via solution process," 2021. [Online]. Available: https://confit.atlas.jp/guide/event-img/idw2019/AMDp1-9/public/pdf_archive?type=in.
[44] X. Li, D. Geng, M. Mativenga, and J. Jang, "High-Speed Dual-Gate a-IGZO TFT-Based Circuits With Top-Gate Offset Structure," IEEE Electron Device Letters, vol. 35, no. 4, pp. 461-463, 2014, doi: 10.1109/LED.2014.2305665.
[45] Y. Zhang, H. Yang, H. Peng, Y. Cao, L. Qin, and S. Zhang, "Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO2 Gate Dielectric for Low-Voltage Applications," IEEE Electron Device Letters, vol. 40, no. 9, pp. 1459-1462, 2019, doi: 10.1109/LED.2019.2931358.
[46] S. Samanta, U. Chand, S. Xu, K. Han, Y. Wu, C. Wang, A. Kumar, H. Velluri, Y. Li, X. Fong, A. V. Y. Thean, and X. Gong, "Low Subthreshold Swing and High Mobility Amorphous Indium–Gallium–Zinc-Oxide Thin-Film Transistor With Thin HfO2 Gate Dielectric and Excellent Uniformity," IEEE Electron Device Letters, vol. 41, no. 6, pp. 856-859, 2020, doi: 10.1109/LED.2020.2985787.
[47] Q. Li, W. Zhao, Q. Hu, C. Gu, S. Zhu, H. Liu, R. Huang, and Y. Wu, "First Demonstration of Sequential Integration for Stacked Gate-All-Around a-IGZO Nanosheet Transistors with Record Id = 2.05 mA/µm, gm = 1.13 mS/µm and Ultralow SS = 66 mV/dec," in 2023 International Electron Devices Meeting (IEDM), 9-13 Dec. 2023 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413891.
[48] S. H. Oh, C. H. Lee, H. T. Kim, J. I. Park, M. J. Kim, S. J. Park, S. G. Im, S. H. Cho, and B. J. Cho, "Overcoming Performance Limitation of IGZO FET by iCVD Fluorine Doping," presented at the 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024.
[49] W. S. Liu, C. H. Hsu, Y. Jiang, Y. C. Lai, and H. C. Kuo, "Improving Device Characteristics of Dual-Gate IGZO Thin-Film Transistors with Ar-O(2) Mixed Plasma Treatment and Rapid Thermal Annealing," Membranes (Basel), vol. 12, no. 1, Dec 30 2021, doi: 10.3390/membranes12010049.
[50] L. Lu, Z. Xia, J. Li, Z. Feng, S. Wang, H. S. Kwok, and M. Wong, "A Comparative Study on Fluorination and Oxidation of Indium–Gallium–Zinc Oxide Thin-Film Transistors," IEEE Electron Device Letters, vol. 39, no. 2, pp. 196-199, 2018, doi: 10.1109/led.2017.2781700.
[51] S. Hooda, C. K. Chen, M. Lal, S. H. Tsai, E. Zamburg, and A. V. Y. Thean, "Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation," in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 11-16 June 2023 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185266.
[52] Y. Liu and T. Li, "High-performance Ultrathin ITO Thin-Film Transistor With Ultralow Subthreshold Swing," in 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 22-25 Oct. 2024 2024, pp. 1-3, doi: 10.1109/ICSICT62049.2024.10831000.
[53] "List of Instruments and Equipment at the Taiwan Semiconductor Research Institute, Hsinchu." https://www.tsri.org.tw/tw/tech/equipment_hsinchu.jsp (accessed.
[54] S. Klassen, "The Photoelectric Effect: Reconstructing the Story for the Physics Classroom," Science & Education, vol. 20, no. 7-8, pp. 719-731, 2009, doi: 10.1007/s11191-009-9214-6.
[55] T. T. T. Nguyen, O. Renault, B. Aventurier, G. Rodriguez, J. P. Barnes, and F. Templier, "Analysis of IGZO Thin-Film Transistors by XPS and Relation With Electrical Characteristics," Journal of Display Technology, vol. 9, no. 9, pp. 770-774, 2013, doi: 10.1109/JDT.2013.2280842.
[56] J. T. Jang, D. Ko, S. J. Choi, D. M. Kim, and D. H. Kim, "Observation of Hydrogen-Related Defect in Subgap Density of States and Its Effects Under Positive Bias Stress in Amorphous InGaZnO TFT," IEEE Electron Device Letters, vol. 42, no. 5, pp. 708-711, 2021, doi: 10.1109/LED.2021.3066624.
[57] G. Yan, H. Yang, W. Liu, N. Zhou, Y. Hu, Y. Shi, J. Gao, G. Tian, Y. Zhang, L. Fan, G. Wang, G. Xu, J. Bi, H. Yin, C. Zhao, and J. Luo, "Mechanism Analysis of Ultralow Leakage and Abnormal Instability in InGaZnO Thin-Film Transistor Toward DRAM," IEEE Transactions on Electron Devices, vol. 69, no. 5, pp. 2417-2422, 2022, doi: 10.1109/TED.2022.3159266.
[58] M. P. Jallorina, J. P. Bermundo, Y. Ishikawa, and Y. Uraoka, "Low temperature (150°C) wet oxygen annealing of amorphous InGaZnO thin-film transistors for flexible device applications," in 2017 24th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), 4-7 July 2017 2017, pp. 203-204.
[59] R. Kishore, K. Vishwakarma, and A. Datta, "Impact of Nonuniform Ozone Anneal Treatment on the Resistance Levels in an IGZO-ReRAM Fabricated on ITO-Coated Glass Substrate," IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6087-6093, 2021, doi: 10.1109/TED.2021.3121231.
[60] K. Han, Q. Kong, Y. Kang, C. Sun, C. Wang, J. Zhang, H. Xu, S. Samanta, J. Zhou, H. Wang, A. V. Y. Thean, and X. Gong, "Indium-Gallium-Zinc-Oxide (IGZO) Nanowire Transistors," IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6610-6616, 2021, doi: 10.1109/TED.2021.3113893.
[61] S. W. Chang, H. H. Hu, C. W. Wu, W. H. Lu, W. H. Lee, and Y. J. Lee, "Sub-μm Gate-All-Around-Like Amorphous-InGaZnO Transistors With Record-High fT of 2.09 GHz," IEEE Transactions on Electron Devices, vol. 71, no. 8, pp. 4710-4716, 2024, doi: 10.1109/TED.2024.3421185.
[62] B. M. Basol and A. Joshi, "Differential Hall Effect Metrology for Electrical Characterization of Advanced Semiconductor Layers," Metrology, vol. 4, no. 4, pp. 547-565, 2024, doi: 10.3390/metrology4040034.
[63] W. Sun, "Principles of Atomic Force Microscopy," in Atomic Force Microscopy in Molecular and Cell Biology, J. Cai Ed. Singapore: Springer Singapore, 2018, pp. 1-28.