| 研究生: |
李恩瑞 Li, En-Jui |
|---|---|
| 論文名稱: |
陽極氧化鋁應用於堆疊式快閃記憶體電荷捕捉層之研究 Study of Anodic Aluminum Oxide Applied in Charge Trapping Layer of Stacked Gate Flash Memory |
| 指導教授: |
洪茂峰
Houng, Mau-Phon |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2005 |
| 畢業學年度: | 93 |
| 語文別: | 中文 |
| 論文頁數: | 82 |
| 中文關鍵詞: | 陽極氧化鋁 、快閃記憶體 |
| 外文關鍵詞: | Anodic Aluminum Oxide, Flash Memory |
| 相關次數: | 點閱:83 下載:1 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
近年來,快閃式記憶體廣泛地應用於可攜式電子產品的資料儲存上,如數位相機與筆記型電腦。隨著積體電路積極度增加以及元件尺寸不斷縮小,傳統懸浮閘極式快閃記憶體因為其結構和可靠度問題將面臨微縮瓶頸,因此許多不同類型的快閃記憶元件被發表,目前最被看好可望成為新一代快閃記憶元件的有SONOS以及奈米晶格等元件;論文中針對SONOS元件在研究過程遇到的電荷捕捉效率不高問題為主,以陽極氧化成長之氧化鋁取代元件中的氮化矽層,實驗結果由此方法成長之氧化鋁有較高的捕捉電荷密度,經過退火處理將捕捉電荷密度減少接著施以外加偏壓,我們發現以陽極氧化鋁為電荷捕捉層的元件較SONOS有明顯的臨界電壓偏移現象,且偏移量與元件退火前後的捕捉電荷量差值呈正比關係,因此我們認為在製程中形成的缺陷在退火處理後成為電荷捕捉中心而增加元件電荷捕捉效率。
Recently, the Flash memory has received much attention for application to the digital cameras and notebook as portable mass storage. With the development of integrated circuit and scaling of device, the conventional floating-gate flash memory has its choke point because of the reliability and cell structure. Now, many researchs on various type of flash cell are proceeding to solve this problem and two major case of them are SONOS and Nano-Crystal flash cell. In this thesis we will focus on the insufficient charge trapping of SONOS cell and take the Anodic Aluminum Oxide (AAO) to substitute for the silicon nitride of SONOS. The experiment result show that OAO- stacked have more initial charge density and we can decrease it with annealing treatment. Under bias, OAO-stacked exhibits superior in shift of threshold voltage compared with SONOS cell and the amount of shift increase with the effect charge density decrease. Then we consider the initial charge formed with process will be a centroid of neutral charge trapping after annealing treatment and responsible for charge trapping with bias supply.
[1] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, “Introduction to
Flash Memory”, Proceedings of the IEEE, vol. 91, no. 4, pp.489-
502, 2003
[2] M. H. White, D. A. Adams, J. Bu, “On the Go with SONOS”, IEEE
Circuits and Devices, vol. 16, no. 4, pp. 22-31, 2000
[3] P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”,
Kluwer Academic Pnblishers
[4] S. M. Sze, “Physics of Semiconductor Devices-Second Edition”,
Central Book Co.
[5] K. J. Lim, M. N. Kim, H. I. Chae, S. H. Kang, M. H. Bae,“Breakdown
and Conduction Phenomena in MIS Structures”, IEEE Transactions on
Electrical Insulator, vol. 27, no. 3, 1992
[6] Z. Weinberg, “On Tunneling in Metal-Oxide-Structures”, J. Appl.
Phys. vol. 53, pp. 5052-5056, 1982.
[7] A. Schenk and G. Heiser, “Modeling and Simulation of Tunneling
through Ultra-thin Gate Dielectrics”, J. Appl. Phys., vol. 81, no.
12, pp. 7900, 1997
[8] J. Kolodzey, E. A. Chowdhury, T. N. Adam, G. Qui, I. Rau, J. O.
olowolafe, J. S. Suehle, Y. Chen, “Electrical Conduction and
Dielectric Breakdown in Aluminum Oxide Insulators on Silicon”,
IEEE Transactions on Electron Devices, vol. 47, no. 1, pp. 121-128,
2000
[9] D. K. Schroder, “Semiconductor Material and Device Characterization-
Second Edition”, Wiley-Interscience
[10] S. W. Huang, J. G. Hwu, “Electrical Characterization and Process
Control of Cost-Effective High-k Aluminum Oxide Gate Dielectrics
Prepared by Anodization Followed by Furnace Annealing”, IEEE
Transactions on Electron Devices, vol. 50, no. 7,pp.1658-1664, 2003
[11] C. S. Kuo, J. F. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, J. G. Hwu,
“High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film
in Nitric Acid Followed by High-Temperature Annealing”, IEEE
Transactions on Electron Devices, vol. 51, no. 6, pp.854-858, 2004
[12] H. Wu, K. R. Hebert,“Electrochemical transients during the initial
moments of anodic oxidation of aluminum”, Electrochimica Acta, vol.
47 pp.1373–1383, 2002
[13] J. Bu, M. H. White, “Improvement in Retention Reliability of SONOS
Nonvolatile MemoryDevices by Two-step High Temperature Deuterium
Anneals”, IEEE Intenational ReliabilityPhysics Symposium, pp. 52-56,
2001
[14] “國家奈米元件實驗室, “積體電路製程技術訓練班講義”, 2004
[15] A. R. Chowdhuri, C. G. Takoudis, “Metalorganic Chemical Vapor
Deposition of Aluminum Oxide on Si: Evidence of Interface SiO2
Formation ”, Applied Physics Letters, vol. 80, no. 22, pp. 4241-
4243, 2002
[16] J. Bu, M. H. White,“Design Considerations in Scaled SONOS Nonvolatile
Memory Devices”, Sherman Fairchild Laboratory, 16A Memorial Dr. E.,
Lehigh University, Bethlehem.
[17] C. M. Compagnoni, D. Ielmini, A. S. Spinelli, A. L. Lacaita, C. Gerardi,
L. Perniola, B. De Salvo, S. Lombarao,“Program/Erase Dynamics and
Channel Conduction in Nanocrystal Memories”, IEEE
[18] M. L. French, C.Y. Yang, H. Sathianathan, M. H. White,“Design and
Scaling of SONOS Multidielectric Device for Nonvolatile Memory
Applications”, IEEE Transactions on Comp. Pack. and Manu. Tech., vol.
17, no. 3, pp 390-397, 1994
[19] T. Ohzone, T. Matsuda, and T. Hori, “Erase/Write Cycle Tests of
n-MOSFET’s with Si-implanted Gate-SiO2”, IEEE Trans. OnElectron
Devices, vol.43, no.9, pp.1374, 1996
[20] K. H. Wu, T. S. Chen, S. C. Hsu and C. H. Kao, “Impact of Nitride
Process Conditions on SONOS Flash Devices”, Journal of Chung-Cheng
Institute Technology, vol. 32, no. 1, pp.73-80, 2003
[21] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y.
Tamura, Y. Sugiyama, T. Nakanishi and H. Tanaka,“Novel Multi-bit SONOS
Type Flash Memory Using a High-k Charge Trapping Layer”, Symposium on
VLSI Technology Digest of Technical Papers, pp. 27-28, 2003
[22] M. Specht, H. Reisinger, M. Stadele, F. Hofmann, A. Gschwandtner, E.
Landgraf, R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskomfeld, W.
Rosner, J. Kretz, L. Risch,“Retention Time of Novel Charge Trapping
Memory Using Al2O3 Dielectrics”, Infineon Technologies AG, Corporate
Research CPR ND, Memory Products MP INN, pp. 155-158, 2003
[23] X. Wang, J. Liu, W. Bai and D. L. Kwong,“A Novel MONOS-Type Nonvolatile
Memory Using High-k Dielectrics for Improved Data Retention and
Programming Speed”, IEEE Transactions on Electron Devices, vol. 51, no.
4, pp.597-602, 2004
[24] P. Pavan, R. Bez, P. Olovo and E. Zanoni,“Flash Memory Cells-An
Overview”, Proceedings of the IEEE, vol. 85, no. 8, 1997
[25] Z. A. Weinberg, K. J. Stein, T. N. Nguyen and J. Y, Sun,“Ultrathin
Oxide-Nitride-Oxide films”, Appl. Phys. Lett. Vol.57, no.12, pp.1248-
1250, 1990
[26] L. K. Han, M. Bhat, D. Wristers, J. Fulford and D. L. Kwong,“Polarity
Dependence of Dielectric Breakdown in Scaled SiO2”, IEDM Tech. Dig.,
pp.617-620, 1994
[27] S. Mori, E. Sakagami, H. Araki, Y. Kaneko, K. Narita, Y. Ohshima,
Norihisa Arai and K. Yoshikawa,“ONO Inter-Poly Dielectric Scaling for
Nonvolatile Momory Applications”, IEEE Transactions on Electron Devices,
vol.38, no.2, pp. 386-391, 1991
[28] S. Mori, N. Arai, Y. Kaneko and K. Yoshikawa,“Polyoxide Thinning
Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory
Devices”, IEEE Transactions on Electron Devices, vol.38, no.2, pp.270-
277, 1991
[29] C. S. Pan, K. J. Wu, P. P. Freiberger, A. Chatterjee and G. Sery,“A
Scaling Methodology for Oxide-Nitride-Oxide Interpoly Dielectric for
EPROM Applications”, IEEE Transactions on Electron Devices, vol.37,
no.6, pp.1439-1443, 1990
[30] K. Wu, C. S. Pan, J. J. Shaw, P. Freiberger and G. Sery,“A Model for
EPROM Intrinsic Charge Loss through Oxide-Nitride-Oxide(OXO) Interpoly
Dielectric”, IEEE IRPS, pp. 145-149, 1990
[31] S. Mori, Y. Y. Araki, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K.
Yoshikawa, N. Arai, E. Sakagami,“Thickness Scaling Limitation Factors
of ONO Interpoly Dielectric for Nonvolatile Memory Devices”, IEEE
Transactions on Electron Devices, vol.43, no.1, pp.47-53, 1996
[32] 黃禎毅, “多晶矽間的氧化層-氮矽化合物-氧化層對堆疊閘極式快閃記憶體電荷流失
之影響”,成功大學微電子研究所,2002
[33] Z.H.Liu et al., “Characterization of charge trapping and high-field
endurance for 15nm thermally nitrided oxides”, IEEE ED, vol.38, p.344-
354, 1991
[34] K.S.Lim and C.H.Ling, “Charge trapping in interpoly ONO film”, ICSE’98
Proc, p.42, 1998