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研究生: 李恩瑞
Li, En-Jui
論文名稱: 陽極氧化鋁應用於堆疊式快閃記憶體電荷捕捉層之研究
Study of Anodic Aluminum Oxide Applied in Charge Trapping Layer of Stacked Gate Flash Memory
指導教授: 洪茂峰
Houng, Mau-Phon
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 82
中文關鍵詞: 陽極氧化鋁快閃記憶體
外文關鍵詞: Anodic Aluminum Oxide, Flash Memory
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  •   近年來,快閃式記憶體廣泛地應用於可攜式電子產品的資料儲存上,如數位相機與筆記型電腦。隨著積體電路積極度增加以及元件尺寸不斷縮小,傳統懸浮閘極式快閃記憶體因為其結構和可靠度問題將面臨微縮瓶頸,因此許多不同類型的快閃記憶元件被發表,目前最被看好可望成為新一代快閃記憶元件的有SONOS以及奈米晶格等元件;論文中針對SONOS元件在研究過程遇到的電荷捕捉效率不高問題為主,以陽極氧化成長之氧化鋁取代元件中的氮化矽層,實驗結果由此方法成長之氧化鋁有較高的捕捉電荷密度,經過退火處理將捕捉電荷密度減少接著施以外加偏壓,我們發現以陽極氧化鋁為電荷捕捉層的元件較SONOS有明顯的臨界電壓偏移現象,且偏移量與元件退火前後的捕捉電荷量差值呈正比關係,因此我們認為在製程中形成的缺陷在退火處理後成為電荷捕捉中心而增加元件電荷捕捉效率。

      Recently, the Flash memory has received much attention for application to the digital cameras and notebook as portable mass storage. With the development of integrated circuit and scaling of device, the conventional floating-gate flash memory has its choke point because of the reliability and cell structure. Now, many researchs on various type of flash cell are proceeding to solve this problem and two major case of them are SONOS and Nano-Crystal flash cell. In this thesis we will focus on the insufficient charge trapping of SONOS cell and take the Anodic Aluminum Oxide (AAO) to substitute for the silicon nitride of SONOS. The experiment result show that OAO- stacked have more initial charge density and we can decrease it with annealing treatment. Under bias, OAO-stacked exhibits superior in shift of threshold voltage compared with SONOS cell and the amount of shift increase with the effect charge density decrease. Then we consider the initial charge formed with process will be a centroid of neutral charge trapping after annealing treatment and responsible for charge trapping with bias supply.

    第一章 緒論 1-1 研究背景...............1 1-2 研究動機................2 第二章 理論背景 2-1 堆疊式記憶體操作原理.........6 2-2 介電層內載子傳輸機制.........8 2-3 介電層缺陷電荷............13 2-4 介電層崩潰..............14 第三章 實驗流程 3-1 基板清洗...............17 3-2 介電層成長..............18 3-3 介電層退火..............19 3-4 定義正面電極.............20 3-5 背面氧化層蝕刻............21 3-6 背面電極製作.............21 3-7 元件量測...............22 第四章 介電層電性實驗結果與討論 4-1 二氧化矽電性探討...........23 4-2-1 電流機制...............23 4-2-2 缺陷電荷密度.............25 4-2-3 崩潰特性...............26 4-2 氧化鋁電性探討............27 4-3-1 電流機制...............27 4-3-2 FTIR及XRD分析............28 第五章 二氧化矽-氧化鋁-二氧化矽堆疊介電層電 荷捕捉特性 5-1 厚度設計考量...............30 5-2 底部氧化層與氧化鋁接面電荷傳輸機制....31 5-3 臨界電壓漂移情形.............33 5-4 捕捉電荷密度與中心位置..........34 第六章 結論

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