本論文探討利用有機金屬氣相磊晶方法，將奈米結構之砷化鎵與砷化銦化合物半導體選擇性成長於具有二氧化矽之奈米圖案化矽基板。以理論模型推測，隨著圖案化矽基板的圖案大小縮減至奈米尺寸，有助於減輕磊晶層之應力累積並且降低磊晶層的缺陷密度。以晶體結構推測，磊晶層的差排缺陷容易沿著最低能量晶格平面堆疊。因此，我們可將磊晶層成長於奈米圖案之矽基板，並配合奈米尺寸的二氧化矽圖案來降低磊晶層缺陷密度。以實驗結果驗證，砷化鎵磊晶成長於55奈米二氧化矽圓孔陣列之矽基板，可得到蝕刻缺陷密度約為每平方公分 3.3 × 10^5 的磊晶表面。在結晶品質分析方面，相較於磊晶成長於傳統平面矽基板，我們利用55奈米二氧化矽圓孔陣列之矽基板，可將X光繞射儀與光激發螢光量測圖譜的半高全寬值可分別降低39.6 % 與 31.4 %。在二氧化矽圖案的立體幾何形狀方面，相較於方形二氧化矽圖案，我們利用凸狀二氧化矽圖案可進一步降低磊晶層的聚合缺陷，並可進一步降低11.5 % 的X光繞射圖譜之半高全寬值。
我們也將砷化鎵與砷化銦成長於奈米條紋圖案化矽基板。經由蝕刻缺陷製備來分析磊晶表面缺陷密度。相較於砷化鎵磊晶成長於傳統平面矽基板每平方公分高達109的蝕刻缺陷密度，我們將磊晶層成長於奈米條紋圖案化矽基板其磊晶層表面則幾乎沒有蝕刻缺陷產生。經由穿遂式電子顯微鏡分析驗證，我們利用深寬比大於2.04的奈米條紋圖案化基板，幾乎可將全部缺陷侷限於凹槽之中。此外，我們將砷化銦成長於奈米條紋圖案化矽基板也可得到幾乎沒有蝕刻缺陷的磊晶層表面。經由繞射圖譜分析，可得到砷化鎵與砷化銦磊晶層的晶格長度數值分別為5.63 Å 與6.04 Å。此晶格長度數值接近未受應力之砷化鎵與砷化銦材料的晶格常數數值。此結果也應證了利用奈米尺寸圖案化矽基板有助於減輕磊晶層之應力累積。
此外，我們在幾乎無裂痕的磊晶層表面上研製金屬–半導體–金屬型紫外光檢測器。在偏壓5伏特時，其暗電流為1.5×10^-11 安培，其紫外光與可見光的抑制電流比為1479。

GaAs and InAs are grown on geometric nanopatterned and nanoscale stripe patterned Si substrates with SiO2 as a mask by metal–organic vapor–phase epitaxy. Theoretical models suggest the possibility of strain relief and dislocation reduction via a decrease in the initial epitaxial areas to the nanoscale regime. Threading dislocations, which are stacked on the lowest–energy facet plane, are trapped by the SiO2 patterns, reducing the number of dislocations. For GaAs on a 55–nm round–hole patterned Si substrate with SiO2 as a mask, the etching pit density of the GaAs surface is about 3.3 × 10^5 cm^-2. Compared with the full width at half maximum measurement (FWHM) from X–ray diffraction (XRD) ω/2θ scans patterns and photoluminescence spectra of GaAs on a planar Si (001) substrate, those of GaAs on the 55–nm round–hole patterned Si substrate are reduced by 39.6 % and 31.4 %, respectively. The use of 70–nm–wide SiO2 convex–top patterns can suppress the coalescence dislocations of the epi–layer and lead to a further decrease the FWHM values of the XRD ω/2θ scan patterns by 11.5 % compared to those obtained with 70–nm–wide rectangular–top SiO2 patterns.
Compared with the conventional planar Si substrate, depositing the epi–layers onto nanoscale stripe patterned Si substrates decreases the dislocation density from about 109 cm-2 to almost zero. With the aspect ratio increased from 0.44 to 2.04, the etching defect pit density can be significantly decreased. Almost etching–pit–free surfaces of GaAs and InAs nanofins are achieved using nanoscale stripe patterned Si (001). The lattice constants measured from the GaAs and InAs nanofins are 5.63 Å and 6.04 Å, respectively, which are similar to those of natural GaAs and InAs.
An ultraviolet metal–semiconductor–metal photodetector was prepared on an almost crack–free epi–layer surface. With a 5–V applied bias, the UV–to–visible rejection ratio was estimated to be 1479 and the measured leakage current was 1.5×10^-11 A.

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Chapter 5
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Chapter 6
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