近年來，由於資訊產業的迅速發展，多媒體電子系統得到了快速的進步。在數位相機影像重建的過程中，彩色濾波陣列插補法或稱解馬賽克法是關鍵的技術之一。而許多的消費型電子產品需要使用此技術來顯示影像和/或影片。對於許多需要滿足即時處理的應用而言，VLSI硬體實作的解馬賽克技術是必要且必需被考慮的。然而對消費者來說，價格往往是他們選擇消費型電子產品最重要的考量。因此我們希望在本論文中開發出有成本效益的硬體實現。
針對解馬賽克的主題，我們提出一個低成本的去馬賽克方法，用來當作暫存緩衝區的記憶體列數只需二列。此方法使用方向色差設計出一個簡單的邊緣檢測器來辨認每個需插補通道的邊緣方向，並利用此資訊來重建遺失的色彩通道。在與過去所提出的低成本技術相比，我們的方法在主客觀數據上都有較好的表現。雖然與過去所提出的低成本技術相比皆有良好的效果，但是與高品質軟體實現的方法相比，所提出的方法表現較差。因此，我們提出另一種兼顧成本，又有高品質效果的去馬賽克方法。此方法用來當作暫存緩衝區的記憶體列數為四列，並利用最靠近的通道值來求出色差平面，接著利用此平面來抓取邊緣資訊和插補失去的通道。在我們廣泛的實驗下，所提出的技術可保留邊緣特徵，因此在與過去所提出的硬體和軟體實現的方法相比皆可展現出良好的效果。此外，我們使用Verilog 硬體描述語言設計了五階的管線化架構，並利用SYNOPSYS 的 Design Vision 和 TSMC 0.18-μm 標準元件庫進行合成。合成結果顯示，此電路可達到每秒200百萬的處理速度。
這兩種方法只使用簡單的運算(加法器，減法器，移位器以及比較器)，固定的工作視窗，並且不需事前訓練資料和迭代運算。因此，非常適合運用在消費性電子產品上。

Recently, multimedia electronic systems have been quickly growing with the rapid progress of the information industry. Color filter array interpolation, also known as demosaicking and ‘debayering’, is a crucial process for image reconstruction in digital still cameras. Many consumer electronic products need a reconstruction technique to restore the captured photos and/or videos. For practical real-time applications, the very-large-scale integration implementation of demosaicking process is necessary and should be considered. For customers, the cost is usually the most important issue while choosing consumer electronic products. We hope to focus on cost-effective implementation in this dissertation.
On the demosaicking topic, we propose a low-cost demosaicking method. It only uses the two-line-memory buffer. The algorithm employs a simple edge calculator to recognize the edge direction of each processing channel by using directional color differences and uses the information to reconstruct the missing color channels. Compared with the previous low-cost techniques, our method performs better in terms of both quantitative evaluation and visual quality. However, compared with the previous high-quality software implementations, the proposed method performs slightly poorer. Therefore, we propose another demosaicking method. The method not only considered the cost but also exhibited high image quality performance. The required line buffering of the proposed design is four lines. It uses nearest neighboring channels to generate the color difference planes and uses the map to catch the edge information and interpolate missing color channels. Our extensive experiments revealed that the proposed technique preserved edge features and exhibited excellent quantitative evaluation and visual quality performances. Compared with the previous hardware and software implementations, the proposed design achieved superior image qualities. The five-stage very-large-scale integration architecture was implemented by using Verilog hardware description language and synthesized using the SYNOPSYS Design Vision with Taiwan Semiconductor Manufacturing Company 0.18-μm process standard cell library. The synthesis results revealed that the processing rate of proposed design can yield approximately 200 M samples per second.
The two methods all use simple operations (addition, subtraction, shift, and comparator), a fixed local window size and requires no previous training and no iterations. Therefore, they are appropriate for many consumer electronic products.

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