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研究生: 邱茂為
Chiou, Mao-Wei
論文名稱: 玻璃基板上成長新型高性能氧化鋅雙層通道/堆疊絕緣層透明薄膜電晶體之研究
A Novel High Performance ZnO-based Double Channel Transparent Thin Film Transistor with HighκStack Gate on Glass Substrate
指導教授: 方炎坤
Fang, Yean-Kuen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 97
中文關鍵詞: 透明薄膜電晶體濺鍍雙層通道氧化鋅
外文關鍵詞: TTFT, sputtering, double channel, Zinc oxide
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  • 本論文研究在一般玻璃基板上成長大面積平面顯示器用高性能氧化鋁/氧化鉿(Al2O3/HfO2)堆疊絕緣層下閘極增強式(enhancement-mode)氧化鋅雙層通道透明薄膜電晶體。我們使用氧化鋅/氧化鋅鎂為通道層,並用氧化鋅鋁來做源極與汲極。電晶體製作皆使用射頻磁控濺鍍 (Radio Frequency magnetron sputtering)沉積在室溫下完成。氧化鋁和氧化鉿組成的雙層閘極絕緣能有效降低閘極漏電流。氧化鋅摻雜鎂可以加寬能隙及增加電阻率故用來作為上通道層以降低薄膜電晶體的關電流(off-current)。下通道主要作為電晶體導通時的路徑,故使用具有高導電度的純氧化鋅來增加開電流(on-current)。藉由雙層通道的設計可以同時降低off-current及提高開關電流比。
    藉由調整厚度比例的雙層通道及使用堆疊堆疊絕緣層,吾人找出最佳的元件(W/L =500µm/50µm)特性,為:透明度>80%,最小的關電流為1.91×10-10A,最大開關電流比為6.86×106及場效載子遷移率約為2 cm2/Vs。相較於傳統單層閘極絕緣及單層通道氧化鋅薄膜電晶體,雙層通道及雙層閘極絕緣者可提高100倍開關電流比。比起一般以發表的透明氧化鋅薄膜電晶體皆需具有耐高溫的玻璃基板,本研究所發展出的雙層通道及雙層閘極絕緣透明式氧化鋅薄膜電晶體不但性能高,且擁有單一製程及可在室溫下於一般玻璃基板成長的製作簡便及成本低的優點,故更適合於未來大型尺寸平面顯示器的運用。

    In this thesis, an enhancement-mode Zinc oxide (ZnO)-based and bottom gate double channel transparent thin film transistor (TTFT) with Al2O3/ HfO2 stack gate is developed on glass substrate. We use the ZnO based materials for all of layers i.e., ZnO/ZnO:Mg as active layer, Al2O3/ HfO2 as gate dielectric and ZnO:Al as source-drain electrode. Besides, all of layers are deposited by RF magnetron sputtering at room temperature.
    The high κ stack gate including Al2O3 and HfO2 could effectively suppress gate leakage current. Besides, ZnO:Mg and ZnO are used respectively as top and button channel. The ZnO:Mg is ZnO doped with Mg , which could increase energy gap and resistivity, thus reducing the off current, and resulting in a higher on-off current ratio. By optimizing the top/ button channel thickness and use of the high κ stack gate, we obtain the performances of the TFT as; field-effect mobility ~ 2 cm2/Vs , minimum off current ~1.91×10-10A, on-off current ratio ~6.86×106, optical transparency >80%.Compare to the reported ZnO based transparent TFTs prepared on special glass substrates, the developed highκ stack gate double channel ZnO TFT has the advantages of simpler preparation and lower cost, thus is more suitable for future advanced large dimension flat panel display applications.

    中文摘要I 英文摘要 III 誌 謝 V 目錄 VII 圖表目錄XI 第一章 導論 1 1-1 前言 1 1-2 論文架構 4 第二章 理論基礎 5 2-1濺鍍理論 5 2-1-1 濺射現象 5 2-1-2 輝光放電(Glow Discharge) [29] 6 2-1-3 沉積現象 7 2-2氧化鋅薄膜結構與性質 8 2-3薄膜電晶體基本結構 9 2-4薄膜電晶體工作原理 10 2-4-1 汲極電流相對於汲極電壓的I-V曲線 10 2-4-2 汲極電流相對於閘極電壓的I-V曲線 12 2-5 薄膜電晶體電性參數 13 第三章實驗方法與步驟 17 3-1磁控濺鍍系統 17 3-1-1 射頻濺射 17 3-1-2 反應性濺射 18 3-1-3 磁控濺鍍理論 19 3-2 薄膜分析量測儀器 20 3-2-1 掃瞄式電子顯微鏡 (Field Emission Scanning Electron Microscope, FE-SEM) 20 3-2-2 原子力顯微鏡 (Atomic Force Microscope, AFM) 21 3-2-3 X光繞射儀 (X-ray Diffrcatometer, XRD) 21 3-2-4 霍爾量測 (Hall Measurement) 22 3-2-5 膜厚量測儀 (α-Step) 23 3-3 實驗流程 23 3-3-1 基板製作與清洗 24 3-3-2 薄膜濺鍍 24 3-3-3薄膜電晶體製作 25 第四章 薄膜分析與討論 26 4-1 薄膜分析 26 4-2 氣體流量與絕緣層品質 26 4-2-1 不同氧氣流量對氧化鉿薄膜漏電流影響 27 4-2-2 不同氧氣流量對氧化鉿薄膜表面形態的影響 28 4-2-3堆疊氧化鋁/氧化鉿薄膜降低漏電流 28 4-3 氧化鋅薄膜分析 29 4-3-1 濺鍍功率對氧化鋅鎂的影響 29 4-3-2 純氧化鋅與氧化鋅鎂的比較 30 4-3-3 濺鍍功率對氧化鋅鋁的影響 31 第五章 氧化鋅透明薄膜電晶體 分析與討論 33 5-1選擇適合參數薄膜電晶體製作與量測 33 5-2 比較單絕緣層與堆疊絕緣層元件 34 5-2-1 絕緣層材料特性 34 5-2-2單絕緣層與堆疊絕緣層元件特性比較 34 5-3 探討雙通道層元件:調變上下通道層厚度比例 35 5-3-1 使用氧化鋅鎂作為通道層之結構 35 5-3-2 不同厚度比例之雙通道層元件 36 5-4 探討單雙通道層元件特性 36 第六章 結論與未來展望 38 6-1 結論 38 6-2 未來展望 40 參考文獻 41 附表 48 附圖 50

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