成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	陳建佑 Chen, Jan-Yow
論文名稱：	不同通道寬度之N型金氧半電晶體其與熱載子可靠度研究 Characteristics and hot carrier reliability of n-type MOS transistor with difference channel width
指導教授：	陳志方 Chen, Jone-Fang
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 微電子工程研究所 Institute of Microelectronics
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	95
中文關鍵詞：	熱載子、窄通道、電晶體、可靠度
外文關鍵詞：	hot-carrier, narrow channel, transistor, reliability
相關次數：	點閱：65 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在現今CMOS技術中，淺溝槽絕緣(STI)不可避免地使用於相鄰電晶體間的絕緣，但其對於熱載子(HC)可靠度的影響，至今仍未確定，特別是窄寬度的n-MOSFET。
在本研究論文中，採用業界先進製程，通道長度為0.24μm和0.06μm，閘極氧化層厚度為40Å與20Å，寬度分別為10μm、5μm、3μm、1μm與0,07μm之n-MOSFET作為實驗樣本，並進行熱載子(HC)加壓測試。實驗前後，皆對電晶體量測I-V等特性，藉以分析其物理特性及熱載子(HC)效應。
經由熱載子實驗量測後，與寬通道元件比較，窄通道n-MOSFET所產生之介面狀態和氧化層陷入電荷較多，推測是有一個較大垂直電場，使得在通道邊緣區域熱載子注入率增加，而使其電晶體性能加速退化。然後利用charge pumping方法可以找出其退化原因所造成不同的結果。
最後計算寬通道與窄通通元件lifetime，比較lifetime後可以得知窄通道元件有較小的壽命，我們也更加確認無論是考慮性能或者是熱載子可靠度，窄寬度元件都具有相當大的影響。

Shallow trench isolation (STI) is inevitable to be used in isolating the neighboring transistors in today CMOS technology, but their influences on hot-carrier (HC) reliability is not clear especially on the narrow width n-MOSFETs.
In this work, n-MOSFETs on wafers from advanced technology were characterized. The n-MOSFETs used in this experiments have L = 0.24μm and 0.06μm, W = 10μm、5μm、3μm、1μm and 0.07μm with 40Å and 20Å gate oxide thickness. After experiments, I-V measurements were used to characterize the physical properties and hot-carrier (HC) effects of these devices.
After hot carrier stress experiment on wide channel with narrow channel devices, comparing with the wide width n-MOSFETs, the experimental results discovered that the narrow width n-MOSFETs have more degradation by the generations of interface states and oxide trapped charges. It is presumable that a high vertical electric field in the channel edge region causes the increasing of the hot-carrier injection (HCI) rate. Charge pumping method is used to confirm the devices different degradation.
At last we study on lifetime issue to compare the device reliability. Comparing with the wide channel n-MOSFETs, the narrow width n-MOSFET have small lifetime, we can conclude that device performance and hot carrier reliability, narrow width n-MOSFET have quite higher impact.

Abstract (Chinese).........................................I
Abstract (English).......................................III
Acknowledgements...........................................V
Contents.................................................VII
Tables Captions............................................X
Figure Captions...........................................XI
Chapter 1 Introduction.....................................2
1 Background and Motivation..............................2
2 Thesis Organization....................................3
Chapter 2 Basics about MOSFETs and Hot-Carrier reliability.6
1 MOSFET Devices.........................................6
2 Hot Carrier Effects....................................6
3 Narrow Width Effect and Inverse Narrow Width Effect....9
Chapter 3 Measurement & Discussions of device characteristics...........................................19
1 Introduction..........................................19
2 Measurement Methodology...............................19
2.1 Measurement setup...................................19
2.2 Id-Vd measurement...................................19
2.3 Id-Vg measurement...................................20
2.4 VT extraction.......................................21
3 Device description....................................21
4 Measurement results...................................21
4.1 IO device characteristic............................22
4.2 Core device characteristic..........................23
5 Summary...............................................23
Chapter 4 Width Effect on Hot-Carrier-Induced Degradation for n-MOS IO devices......................................39
1 Introduction..........................................39
2 Experiment methodology & Stress conditions............40
3 Experimental results..................................40
3.1 Width-dependent hot carrier degradation.............40
3.2 Comparison of the impact ionization rate............41
3.3 VT shift and Idlin degradation analysis.............43
4 Charge pumping analysis...............................44
4.1 Introduction to charge pumping theory...............44
4.2 Experiment..........................................46
4.3 Charge pumping experiment results...................46
5 Result discussions....................................47
6 Summary...............................................47
Chapter 5 Width Effect on Hot-Carrier-Induced Degradation for n-MOS Core devices....................................68
1 Introduction..........................................68
2 Experiment methodology & Stress conditions............69
3 Experimental results..................................69
3.1 Hot carrier stress results..........................69
3.2 Forward and Reverse bias measurement results........70
3.3 STI stress area & STI enhanced hot carrier stress area......................................................71
4 Result discussions....................................72
5 Summary...............................................73
Chapter 6 Conclusion and future work......................86
1 Conclusion............................................86
2 Future work...........................................87
References................................................88
                                    

Chapter 1
[1]K. Hieda, "Effects of a new trench-isolated transistor using sidewall gates," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 36, p. 1615, 1989.
[2]K. Ohe, et al., "Narrow-width effects of shallow trench-isolated CMOS with n+-polysilicon gate," IEEE Trans. Electron Devices, vol. 36, pp. 1110-1116, 1989.
[3]B. S. Doyle, et al., "Comparison of shallow trench and LOCOS isolation for hot-carrier resistance," Electron Device Letters, IEEE, vol. 12, pp. 673-675, 1991.
[4]F. Schuler, et al., "Measurement and modeling of a new width dependence of nmosfet degradation," Microelectronics and Reliability, vol. 36, pp. 1675-1678, 1996.
[5]N. Shigyo and T. Hiraoka, "A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases," Solid-State Electronics, vol. 43, pp. 2061-2066, 1999.
[6]M. won Lee, "Width Edge Effects in Shallow Trench Isolated nMOSFET," 2002.
[7]V. Srinivasan and J. Barnes, "Small width effects on MOSFET hot-electron reliability," 1980.
[8]M. Bourcerie, et al., "Hot-carrier stressing damage in wide and narrow LDD NMOStransistors," IEEE ELECTRON DEVICE LETTERS, vol. 10, pp. 132-134, 1989.
[9]Y. Nishioka, et al., "Channel length and width dependence of hot-carrier hardness influorinated MOSFETs," IEEE ELECTRON DEVICE LETTERS, vol. 10, pp. 540-542, 1989.
[10]H. Hwang, et al., "Hot-carrier reliability characteristics of narrow-width MOSFETs," Solid-State Electronics, vol. 36, pp. 665-666, 1993.
[11]M. Nishigohri, et al., "Anomalous hot-carrier induced degradation in very narrow channel nMOSFETs with STI structure," in Electron Devices Meeting, 1996., International, 1996, pp. 881-884.
[12]W. Lee, et al., "Degradation of hot carrier lifetime for narrow width MOSFET with shallow trench isolation," in Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International, 1999, pp. 259-262.
[13]L. Erhong and S. Prasad, "Channel width dependence of NMOSFET hot carrier degradation," Electron Devices, IEEE Transactions on, vol. 50, pp. 1545-1548, 2003.
[14]C. Mazure, et al., "Width-independent narrow nMOSFET reliability by split-well drive-in," IEEE ELECTRON DEVICE LETTERS, vol. 11, pp. 224-226, 1990.
[15]J. M. P. Jeffrey Mun Pun Yue, "Hot-carrier degradation mechanism in narrow-and wide-channeln-MOSFETs with recessed LOCOS isolation structure," IEEE ELECTRON DEVICE LETTERS, vol. 21, p. 130, 2000.
[16]W. K. Chim, et al., "Hot-Carrier Lifetime Dependence on Channel Width and Silicon Recess Depth in N Channel Metal Oxide Semiconductor Field Effect Transistors with the Recessed Local Oxidation of Silicon Isolation Structure," JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 41, p. 47, 2002.
[17]S. S. Chung, et al., "A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices," in Reliability Physics Symposium, 2001. Proceedings. 39th Annual. 2001 IEEE International, 2001, pp. 419-424.
[18]S. Chung, S., et al., "New Degradation Mechanisms of Width Dependent Hot Carrier Effect in Quarter Micron Shallow Trench Isolated p Channel Metal Oxide Semiconductor Field Effect Transistors," JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 40, p. 69, 2001.
[19]S. G. Lee, et al., "Experimental evidence for nonlucky electron model effect in 0.15um NMOSFETs," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 49, pp. 1876-1881, 2002.

Chapter 2
[1]A. Schwerin, et al., "The relationship between Oxide charge and device degradation: A comparative study of n- and p- channel MOSFET's," Electron Devices, IEEE Transactions on, vol. 34, pp. 2493-2500, 1987.
[2]A. G. Sabnis, "VLSI Reliability, vol. 22 of VLSI Electronics Microstructure Science," ed: San Diego, California: Academic Press, New York, Chapter 6, 1990.
[3]J. Frey, "Where do hot electrons come from? [MOSFETs]," Circuits and Devices Magazine, IEEE, vol. 7, pp. 31-34, 37, 1991.
[4]S. Tam and H. Chenming, "Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's," Electron Devices, IEEE Transactions on, vol. 31, pp. 1264-1273, 1984.
[5]H. Chenming, et al., "Hot-electron-induced MOSFET degradation—Model, monitor, and improvement," Electron Devices, IEEE Transactions on, vol. 32, pp. 375-385, 1985.
[6]M. Chen, et al., "Suppression of hot-carrier effects in submicrometer CMOS technology," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 35, pp. 2210-2220, 1988.
[7]A. Schütz, et al., "A two-dimensional model of the avalanche effects in MOS transistors," Solid-State Electronics, vol. 25, pp. 177-183, 1982.
[8]W. Muller, et al., "Short-channel MOS transistors in the avalanche-multiplication regime," Electron Devices, IEEE Transactions on, vol. 29, pp. 1778-1784, 1982.
[9]F. Hsu, et al., "An analytical breakdown model for short-channel MOSFET's," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 29, pp. 1735-1740, 1982.
[10]S. S. S. Chung and T. C. Li, "An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates," Electron Devices, IEEE Transactions on, vol. 39, pp. 614-622, 1992.
[11]S. K. H. Fung, et al., "Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation," Solid-State Electronics, vol. 41, pp. 1885-1889, 1997.
[12]L. A. Akers, "The inverse-narrow-width effect," Electron Device Letters, IEEE, vol. 7, pp. 419-421, 1986.
[13]C. Pacha, et al., "Impact of STI-induced stress, inverse narrow width effect, and statistical VTH variations on leakage currents in 120 nm CMOS," in Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European, 2004, pp. 397-400.

Chapter 3
[1]M. Nishigohri, et al., "Anomalous hot-carrier induced degradation in very narrow channel nMOSFETs with STI structure," in Electron Devices Meeting, 1996., International, 1996, pp. 881-884.
[2]H. Hwang, et al., "Current-crowding effect in diagona MOSFET's," Electron Device Letters, IEEE, vol. 14, pp. 289-291, 1993.
[3]A. Ono, et al., "TED control technology for suppression of reverse narrow channeleffect in 0.1 μm MOS devices," in Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International, 1997, pp. 227-230.
[4]W. S. Lau, et al., "Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation," in Electron Devices and Solid-State Circuits, 2005 IEEE Conference on, 2005, pp. 773-776.

Chapter 4
[1]H. Hwang, et al., "Current-crowding effect in diagonal MOSFET's," Electron Device Letters, IEEE, vol. 14, pp. 289-291, 1993.
[2]J. Chung, et al., "Hot-electron currents in deep-submicrometer MOSFETs," IEDM Tech. Dig, p. 200¡V203, 1988.
[3]H. Chenming, et al., "Hot-electron-induced MOSFET degradation—Model, monitor, and improvement," Electron Devices, IEEE Transactions on, vol. 32, pp. 375-385, 1985.
[4]E. Takeda, et al., Hot-carrier effects in MOS devices: Academic Pr, 1995.
[5]A. Melik-Martirosian and T. Ma, "Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices," 1999, pp. 93-96.
[6]D. Schroder, Semiconductor material and device characterization: IEEE, 2006.
[7]Y. Chu, et al., "A new charge-pumping technique for profiling the interface-statesand oxide-trapped charges in MOSFETs," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 47, pp. 348-353, 2000.

Chapter 5
[1]X. Liu, et al., "A study of inverse narrow width effect of 65nm low power CMOS technology," in Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, 2008, pp. 1138-1141.
[2]K. Hieda, "Effects of a new trench-isolated transistor using sidewall gates," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 36, p. 1615, 1989.
[3]B. S. Doyle, et al., "Comparison of shallow trench and LOCOS isolation for hot-carrier resistance," Electron Device Letters, IEEE, vol. 12, pp. 673-675, 1991.
[4]S. Geissler, et al., "A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices," in Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International, 1991, pp. 839-842.
[5]F. Schuler, et al., "Measurement and modeling of a new width dependence of nmosfet degradation," Microelectronics and Reliability, vol. 36, pp. 1675-1678, 1996.
[6]M. Miyamoto, "Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 51, p. 440, 2004.
[7]E. Li, et al., "Hot carrier effects in nMOSFETs in 0.1 μm CMOS technology," in Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International, 1999, pp. 253-258.
[8]Y.-H. Lee, et al., "Effect of trench edge on pMOSFET reliability," MICROELECTRONICS RELIABILITY, vol. 41, pp. 689-696, 2001.
[9]T. Ohzone, et al., "A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width," 2006, pp. 187-192.
[10]C. M. Lai, et al., "Width effect on hot-carrier-induced degradation for 90nm partially depleted SOICMOSFETs," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 44, pp. 2361-2365, 2005.

校內：2015-07-06公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

簡易檢索 / 詳目顯示

相關論文