目前廣泛應用的數位簽章標準，如RSA和ECDSA，其安全性是依賴於質因數分解或離散對數問題等特定數學難題之上。然而，隨著近年來量子電腦技術的發展，Shor 演算法使得傳統公鑰密碼系統面臨崩潰的風險。
　　為此，美國國家標準技術研究院（National Institute of Standards and Technology, NIST）於2016年啟動了後量子密碼學（Post-Quantum Cryptography, PQC）標準化流程，徵集並評估全球的候選演算法。經過多年的篩選，NIST在2022年7月宣布了首批入選的標準。其中，CRYSTALS-Dilithium被選為數位簽章演算法的首選標準，並隨後被正式命名為ML-DSA（Module-Lattice-based Digital Signature Algorithm）。
　　在ML-DSA演算法中，不論在現有研究中，或是CRYSTALS-Dilithium團隊的官方文件中，皆提到需大量使用到SHA-3可擴充輸出函數（extendable-output functions, XOFs），也就是SHAKE128和SHAKE256。因此，設計出一個適合的SHA-3可擴充輸出函數模組將對整個演算法系統帶來極大的改善，本研究針對ML-DSA演算法執行特性，利用少許資源便能大幅減少輸入/輸出延遲，提高數位簽章與驗證整體流程的效能。
　　本研究在Xilinx Artix-7與Virtex UltraSacle+ FPGA平台上進行合成與數據比較，與現有表現最佳之ML-DSA高效能研究相比，本研究之SHA-3可擴充輸出函數模組硬體電路，本研究在LUT / FF上分別為其0.83× / 0.45×，在使用到SHA-3模組的各函式上的運行時間僅需其0.25× ~ 0.84×，而在金鑰生成 / 簽署 / 驗證所需的運算時間分別為0.77× / 0.64× / 0.87×，本研究不論在成本抑或是效能上皆有著顯著優勢。

This study targets the operational characteristics of ML-DSA to design a high-performance, optimized hardware architecture for SHA-3 extendable-output functions, significantly reducing input and output latency, enhancing the overall performance of the digital signature and its verification processes.
The proposed design was implemented and synthesized on Xilinx Artix-7 and Virtex UltraScale+ FPGA platforms. Compared to the state-of-the-art ML-DSA implementation, the proposed SHA-3 hardware module requires fewer hardware resources, utilizing only 0.83× the LUTs and 0.45× the FFs. In terms of speed, the execution time for SHA-3 related functions is reduced to between 0.25× and 0.84×. Furthermore, the computation times for the KeyGen, Sign, Verify functions are reduced to 0.77×, 0.64×, 0.87×, respectively, for NIST security level 5.

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