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研究生: 陳思樺
Chen, Si-Hua
論文名稱: 具非等向性矽電容率奈米尺寸金氧半場效電晶體之非平衡態格林函數模擬
NEGF Simulation of Nanoscale MOSFETs with Anisotropic Si Permittivity
指導教授: 高國興
Kao, Kuo-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 79
中文關鍵詞: 緊密束縛模型量子傳輸非平衡態格林函數雙閘極金氧半場效電晶體非等向性介電質非均勻性介電質非等向性電容率非均勻性電容率
外文關鍵詞: Tight-binding (TB), quantum transport, non-equilibrium Green’s function (NEGF), double-gate MOSFETs (DG MOSFETs), anisotropic dielectrics, non-uniform dielectrics, anisotropic permittivity, non-uniform permittivity
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  • 隨著互補式金氧半場效電晶體(CMOS)尺寸的微縮,衍伸出許多需要進一步探討的議題。本論文中採用了非平衡態格林函數(NEGF)求解薛丁格方程式的方法描述在奈米尺寸雙閘極金氧半場效電晶體中,電子的量子傳輸行為,同時藉由將此傳輸方程式與波松方程式求得收斂的自相一致電位值,求得電子密度、傳輸係數及電流,並由此得到閘極電壓與汲極電流的關係曲線。

    量子效應已包含在於電子傳輸方向使用NEGF方法及求解厚度方向(量子侷限方向) 的薛丁格方程式中。除此之外,當元件尺寸夠小,矽本體厚度夠薄時,在厚度方向,實驗上量測到的介電常數值會較塊材為小,理論計算上的預測,為介電質張量(電容率張量),對角線的元素中,描述厚度方向的矩陣元素較塊材為小,矽本體為一非等向性介電質。另一個已提出的模型是,沿著厚度方向,從材料中央到表面,介電常數從塊材的介電常數值逐漸下降,電容率的分佈隨空間而變化,矽本體為一非均勻性介電質。本論文目的旨在探討當矽本體為非等向性介電質及非均勻性介電質時,其電性和當矽本體為一般塊材(為一等向性及均勻介電質)時的差異。

    由計算結果得知,當表面區域的介電常數(電容率)下降時,由於在電子傳輸方向的能障增加,使得在相同偏壓下的電流變小,元件的次臨界擺幅降低且臨界電壓增加,因此較不會受短通道效應的影響。而當在厚度方向(量子侷限方向)的介電常數(電容率)下降時,由於在電子傳輸方向的能障降低,使得在相同偏壓下的電流變小,因此元件的次臨界擺幅增加且臨界電壓上升,較會受短通道效應影響。

    對於長通道元件而言,介電常數(電容率)的變化對於電子傳輸方向之能障的影響較不明顯,因此當介電常數(電容率)下降時,對I-V曲線的影響幾乎可以忽略。

    CMOS scaling has led to several issues that are necessary to be investigated further. In this thesis, the transport behavior of electrons in a nanoscale double-gate (DG) MOSFET is modeled by solving Schrödinger equation in non-equilibrium Green’s function (NEGF) formalism which is solved self-consistently with the Poisson equation to obtain the potential profile, electron density, transmission coefficient and thus, the drain current versus gate voltage (I_DS-V_GS) curves.

    In addition to quantum effects which have been taken into account in the transport equation, the reduction of permittivity in the surface region and the anisotropic permittivity that influence the electrical properties are investigated and their influences on the electrical characteristics of MOSFETs are discussed.

    It is shown that the reduction of permittivity in the surface region slightly improves the subthreshold swing and slightly increases the threshold voltage due to the increase of the potential barrier for electrons in the transport direction. This suggests the better immunity to SCEs for materials of the channel with smaller permittivity. In the case of anisotropic permittivity, the subthreshold swing degrades and the off-leakage current becomes higher as the permittivity in the confinement direction becomes smaller due to the decrease of the potential barrier in the transport direction. This suggests the better immunity to SCEs for materials of the channel with larger permittivity in the confinement direction.

    For long channel devices, the variation in permittivity barely changes the potential barrier in the transport direction. Therefore, the variation in the permittivity has neglecting effects on the (I_DS-V_GS) characteristic.

    摘要 - I Abstract - II 誌謝 - III Contents - IV Table captions - V Figure captions - VI Chapter I Introduction - 1 1-1 MOSFET Scaling - 1 1-2 Quantum Confinement - 5 1-3 Double Gate MOSFETs - 7 1-4 Reduction of Permittivity in Thin Silicon Film - 9 1-5 The Outline and the Objective of the Thesis - 10 Chapter II Theoretical Approach - 12 2-1 Tight-Binding Method - 12 2-2 The Non-Equilibrium Green's Function (NEGF) Formalism - 22 Chapter III The Influence of Isotropic and Uniform Permittivity Reduction on the Electrical Characteristics of Double-Gate MOSFETs - 30 3-1 Device Structure - 30 3-2 Simulation Setup - 32 3-3 Results and Discussion - 33 Chapter IV The Influence of Anisotropic and Non-Uniform Permittivity Reduction on the Electrical Characteristics of Double-Gate MOSFETs - 45 4-1 Device Structure - 45 4-2 Simulation Setup - 47 4-3 Results and Discussion - 53 Chapter V Conclusion and Future Work - 74 5-1 Conclusion - 74 5-2 Future Work - 74 References - 75

    References in chapter 1
    [1] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, Vol. 38, number 8, April 19, 1965
    [2] Isabelle Ferain, Cynthia A. Colinge & Jean-Pierre Colinge, “Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors”, NATURE, VOL 479, 17 NOVEMBER 2011
    [3] ITU, Mark Lipacis, Morgan Stanley Research, http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
    [4] Robert H. Dennard, Fritz H. Gaensslen et al. , “Design of Ion-Implanted MOSFET’S with Very Small Physical Dimensions”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, OCTOBER 1974
    [5] DALE L. CRITCHLOW, “MOSFET Scaling—The Driver of VLSI Technology”, PROCEEDINGS OF THE IEEE, VOL. 87, NO. 4, APRIL 1999
    [6] DAVID J. FRANK, ROBERT H. DENNARD et al., “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001
    [7] J.L. Hop, H.M. Nayfeh et al., “Strained Silicon MOSFET Technology”, Electron Devices Meeting, 2002. IEDM '02. International
    [8] Els Parton and Peter Verheyen, “Strained silicon — the key to sub-45 nm CMOS”, Elsevier, III-Vs Review, Volume 19, Issue 3, April 2006, Pages 28-31
    [9] C.C. Wu, D.W. Lin et al., “High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme”, Electron Devices Meeting (IEDM), 2010 IEEE International
    [10] Jean-Pierre Colinge, “SILICON-ON-INSULATOR TECHNOLOGY: MATERIALS TO VLSI”, Springer Science+Business Media, LLC
    [11] M. Bruel, “Silicon on insulator material technology”, Electronics Letters, Volume: 31, Issue: 14, 6 Jul 1995
    [12] F. D’Agostino, D. Quercia, “Short-Channel Effects in MOSFETs”
    [13] Simon M. Sze, Kwok K. Ng, “Physics of Semiconductor Devices, 3rd Edition”, Wiley
    [14] Moongyu Jang, “Scalability of Schottky barrier metal-oxide-semiconductor transistors”, Nano Convergence (2016) 3:11
    [15] Andy Wei, Melanie J. Sherony, and Dimitri A. Antoniadis, “Effect of Floating-Body Charge on SOI MOSFET Design”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 2, FEBRUARY 1998
    [16] Siau Ben Chiah and Xing Zhou, “Floating-Body Effect in Partially/Dynamically/Fully Depleted DG/SOI MOSFETs Based on Unified Regional Modeling of Surface and Body Potentials”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 2, FEBRUARY 2014
    [17] L. Dreeskornfeld, J. Hartwich et al. “Comparison of partially and fully depleted SOI transistors down to the sub 50nm gate length regime”, Electrochemical Society Proceedings, Vol. 2003-05,p.361,2003
    [18] Eiichi Suzuki, Kenichi Ishii et al. “Highly Suppressed Short-Channel Effects in Ultrathin SOI n-MOSFET’s”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 2, FEBRUARY 2000
    [19] Ran-Hong Yan et al. “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 7, JULY 1992
    [20] Saibal Mukhopadhyay et al, “Optimal UTB FD/SOI Device Structure Using Thin BOX for Sub-50-nm SRAM Design”, IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 4, APRIL 2006
    [21] Stanislav Markov, Niza Mohd Idris, and Asen Asenov, “Statistical Variability in n-channel UTB-FD-SOI MOSFETs under the Influence of RDF, LER, MGG and PBTI”, SOI Conference (SOI), 2011 IEEE International
    [22] Qiang Chen et al. “A Physical Short-Channel Threshold Voltage Model for Undoped Symmetric Double-Gate MOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003
    [23] Yuan Taur, “An Analytical Solution to a Double-Gate MOSFET with Undoped Body”, IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 5, MAY 2000
    [24] Rathnamala Rao et al., “Study of Random Dopant Fluctuation Effects in FD-SOI MOSFET Using Analytical Threshold Voltage Model”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 10, NO. 2, JUNE 2010
    [25] Maria Aboy et al., “Carrier mobility degradation in highly B-doped junctions”, Proceedings of the 2009 Spanish Conference on Electron Devices - Feb 11-13, 2009. Santiago de Compostela, Spain.
    [26] Yogesh Singh Chauhan et al., “BSIM Compact MOSFET Models for SPICE Simulation”, MIXDES 2013, 20th International Conference "Mixed Design of Integrated Circuits and Systems", June 20-22, 2013, Gdynia, Poland
    [27] Jean-Pierre Colinge, “Multi-gate SOI MOSFETs”, Elsevier, Microelectronic Engineering 84 (2007) 2071–2076
    [28] Jean-Pierre Colinge, “FinFETs and Other Multi-Gate Transistors”, Springer
    [29] R. John Bosco Balaguru, B. G. Jeyaprakash, “Quantum Wells, Quantum Wires, Quantum Dots, Quantum Limit of Conductance, Quantum Capacitance & Quantum HALL Effect”, NPTEL – Electrical & Electronics Engineering – Semiconductor Nanodevices
    [30] Supriyo Datta, “Quantum Transport: Atom to Transistor”, CAMBRIDGE
    [31] Lixin Ge and Jerry G. Fossum, “Analytical Modeling of Quantization and Volume Inversion in Thin Si-Film DG MOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002
    [32] Bogdan Majkusiak, Tomasz Janik, and Jakub Walczak, “Semiconductor Thickness Effects in the Double-Gate SOI MOSFET”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998
    [33] Scott A. Hareland et al., “A Computationally Efficient Model for version Layer Quantization Effects in Deep Submicron N-Channel MOSFETs”, IEEE TRANSACTIONS ON ELECTKON DEVICES, VOL. 43, NO. 1, JANUARY 1996
    [34] Scott A. Hareland et al., “ A Physically-Based Model for Quantization Effects in Hole Inversion Layers”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 1, JANUARY 1998
    [35] Tomasz Janik and Bogdan Majkusiak, “Analysis of the MOS Transistor Based on the Self-Consistent Solution to the Schr¨odinger and Poisson Equations and on the Local Mobility Model”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 6, JUNE 1998
    [36] Maarten J. van Dort et al., “Influence of High Substrate Doping Levels on the Threshold Voltage and the Mobility of Deep-Submicrometer MOSFET’s”, IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39, NO. 4, APRIL 1992
    [37] Yasuhisa Omura et al., “Quantum-Mechanical Effects on the Threshold Voltage of Ultrathin-SOI nMOSFET’s”, IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO. 12, DECEMBER 1993
    [38] E. R. Worley, “Theory of the fully-depleted SOS/MOS transistor,” Solid-State Electronics, vol. 23, pp. 1107-1111, 1980
    [39] Qiang Chen, Evans M. Harrell, II, and James D. Meindl, “A Physical Short-Channel Threshold Voltage Model for Undoped Symmetric Double-Gate MOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003
    [40] A. Asenov, J.R. Watling, A.R. Brown and D.K. Ferry, “The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices”, Journal of Computational Electronics December 2002, Volume 1, Issue 4, pp 503–513
    [41] Taur Y. and Ning T.H. 1998. Fundamentals of modern VLSI devices. Cambridge University Press, Cambridge, UK.
    [42] FRANCIS BALESTRA et al. “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance”, IEEE Electron Device Letters ( Volume: 8, Issue: 9, Sep 1987 )
    [43] Gang Zhang, Ming-Bin Yu, Chih-Hang Tung, and Guo-Qiang Lo, “Quantum Size Effects on Dielectric Constants and Optical Absorption of Ultrathin Silicon Films”, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, DECEMBER 2008
    [44] C. Delerue, M. Lannoo, and G. Allan, “Concept of dielectric constant for nanosized systems”, PHYSICAL REVIEW B 68, 115411 (2003)
    [45] Feliciano Giustino and Alfredo Pasquarello, “Theory of atomic-scale dielectric permittivity at insulator interfaces”, PHYSICAL REVIEW B 71, 144104 (2005)
    [46] Stanislav Markov et al., “Permittivity of Oxidized Ultra-Thin Silicon Films from Atomistic Simulations”, IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 10, OCTOBER 2015
    [47] Alexander N. Kholod et al., “Optical properties of Ge and Si nanosheets––confinement and symmetry effects”, ELSEVIER, Surface Science, Volume 527, Issues 1–3, 10 March 2003, Pages 30-40
    [48] Han G. Yoo and Philippe M. Fauchet, “Dielectric constant reduction in silicon nanostructures”, PHYSICAL REVIEW B 77, 115355 (2008)
    [49] Quantum well, Electronic world: http://elektroarsenal.net/quantum-wells.html

    References in chapter 2
    [1] James Patterson and Bernard Bailey, “Solid-State Physics: Introduction to the Theory”, Springer
    [2] Charles Kittel, “Introduction to Solid State Physics”, 6th edition, John Wiley & Sons
    [3] Edward McCann and Mikito Koshino, “The electronic properties of bilayer graphene”, 2013 IOP Publishing Ltd, Reports on Progress in Physics, Volume 76, Number 5
    [4] Hsien-Ching Chung, “Electronic and Optical Properties of Monolayer and Bilayer Graphene Nanoribbons”, doctoral dissertation
    [5] Supriyo Datta, “Nanoscale device modeling: the Green’s function method”, Superlattices and Microstructures, Vol. 28, No. 4, 2000
    [6] Xavier Blase “An introduction to Green’s function in many-body condensed-matter quantum systems”
    [7] Supriyo Datta, “Quantum Transport: Atom to Transistor”, CAMBRIDGE
    [8] Supriyo Datta, “The NEGF Method: Capabilities and Challenges”, Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on
    [9] Supriyo Datta, “Non-equilibrium green's function (NEGF) method: a different perspective”, Computational Electronics (IWCE), 2015 International Workshop on
    [10] Zhibin Ren et al., “nanoMOS 2.5: A Two-Dimensional Simulator for Quantum Transport in Double-Gate MOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003
    [11] Supriyo Datta, “The Non-Equilibrium Green’s Function (NEGF) Formalism: An Elementary Introduction”, Electron Devices Meeting, 2002. IEDM '02. International

    References in chapter 3
    [1] Yu-Feng Hsieh, “Quantum transport modeling for nanoscale MOSFET with non-equilibrium Green’s function formalism”, thesis for Master of Science, National Cheng Kung University
    [2] Zhibin Ren et al., “nanoMOS 2.5: A Two-Dimensional Simulator for Quantum Transport in Double-Gate MOSFETs”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003
    [3] Zhibin Ren et al., “Examination of Design and Manufacturing Issues in a 10 nm Double Gate MOSFET using Nonequilibrium Green's Function Simulation”, Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
    [4] S.M. SzeKwok K. Ng, “Physics of Semiconductor Devices”, S.M. SzeKwok K. Ng
    [5] A. N. M. Zainuddin and A. Haque, “Threshold Voltage Reduction in Strained-Si/SiGe MOS Devices Due to a Difference in the Dielectric Constants of Si and Ge”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

    References in chapter 4
    [1] Stanislav Markov et al., “Permittivity of Oxidized Ultra-Thin Silicon Films from Atomistic Simulations”, IEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 10, OCTOBER 2015

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