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研究生: 楊瓊儀
Yang, Chiung-Yi
論文名稱: L型互補式場效電晶體製程研究與開發
Development and Fabrication of L-shaped Field Effect Transistor (LFET)
指導教授: 王永和
Wang, Yeong-Her
共同指導教授: 李耀仁
Lee, Yao-Jen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 58
中文關鍵詞: 垂直電晶體互補式場效電晶體異質整合
外文關鍵詞: Germanium, vertical field-effect transistor (VFET), complementary field-effect transistor (CFET), heterogeneous integration
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  • 隨著半導體產業發展,元件技術節點逼近物理極限,突破摩爾定律已成為現今主流研究方向,其中主要包含三種方式:第一,持續發展更高密度之元件設計,例如具有多層通道堆疊設計的環繞式閘極電晶體或互補式場效電晶體;第二,改變電晶體結構,例如發展垂直電晶體;第三,開發新的通道材料,例如二維材料的應用。然而,因應未來晶片多功能化的需求,異質材料整合也成為必須面對的課題之一。
    在本論文研究中,將提出一種新型電晶體結構,透過矽與鍺兩種異質通道材料,結合水平電晶體與垂直電晶體形成反相器,該結構形狀如同英文字母「L」,故命名為L型場效電晶體。L型場效電晶體結構使用無接面電晶體技術來抑制短通道效應,相較於互補式場效電晶體,在形成功函數金屬、接觸窗或是異質材料整合等方面都更容易達成。

    With the development of the semiconductor industry, the technology nodes are approaching physical limits. Breaking Moore's Law has become a mainstream research direction today. There are three main methods: First, continue to develop higher-density device designs, such as Gate-All-Around transistors with stacked channels or complementary field-effect transistors; second, changing the transistor structure, such as developing vertical transistors; third, developing new channel materials, such as the application of two-dimensional materials. However, in response to the demand for multi-functional chips in the future, the integration of heterogeneous materials has also become one of the issues that must be faced.
    In this thesis, a new transistor structure, which uses two heterogeneous channel materials, silicon and germanium, to combine lateral transistors and vertical transistors to form an inverter, will be proposed. The structure is shaped like the letter "L." Therefore, it is named L-shaped field effect transistor. The L-shaped field effect transistor uses junctionless transistor technology to suppress short-channel effects. Compared with complementary field-effect transistors, it is easier to form work-function metals and contact windows and integrate heterogeneous materials.

    中文摘要 I Abstract II 致謝 IV Contents V List of Figure VII List of Table IX Chapter 1. Introduction 1 1.1 General Background 1 1.1.1 Moore’s Law & More than Moore 1 1.1.2 The Structure Evolution of Transistor 2 1.1.3 Junctionless Transistor 3 1.2 Vertical Field Effect Transistor 4 1.3 Complementary Field Effect Transistor 8 1.4 L-shaped Field Effect Transistor 11 1.5 Motivation 13 Chapter 2. Device Fabrication and Analyses 15 2.1 Experiment Procedure 15 Figure 2-1 The brief process steps for the LFET. 15 2.1.1 Wafer Preparation 15 2.1.2 N-type Si Layer and P-type Ge Epitaxy Layer 16 2.1.3 Lateral N-type Si Active Region Definition 17 2.1.4 Vertical P-type Ge Active Region Definition 18 2.1.5 Dimension Scaling of the Vertical Ge Pillar 21 2.1.6 Interfacial layer/High-κ/Metal Gate Formation 23 2.1.7 Planarization and Metal Spacer Removal 24 2.1.8 Contact Hole and Metallization 26 2.2 Electrical Characteristics of LFET 28 2.2.1 Lateral N-type Si Transistor 28 2.2.2 Vertical P-type Ge Transistor 29 2.2.3 Voltage Transfer Characteristics of LFET Inverter 30 Chapter 3. Fabrication Challenges and Optimization 31 3.1 Vertical Active Region Formation 31 3.1.1 Lithography of Ge Pillar 31 3.1.2 Dry Etching of Ge Pillar 33 3.2 Planarization 34 3.2.1 Layout Distribution 34 3.2.2 Device Surface Topography 35 3.3 Metal Spacer Removal 36 Chapter 4. Conclusion and Future Work 38 4.1 Conclusion 38 4.2 Future Work 39 4.2.1 Vertical Inversion Mode Transistor 39 4.2.2 Optimization of Metal Spacer Removal 40 Reference 41 簡歷(Vita) 47

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